• Journal of Information Technology Services
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• v.12 no.1
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• pp.1-14
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• 2013

The government has implemented operating the bus information terminal (hereinafter, 'BIT') to use by building it at a major bus station to solve the problem of traffic congestion. Busan Metropolitan City has been continuously expanding the installation of 'BIT' since 2003. However, there are few research on the factor to use and satisfaction survey on 'BIT' from the perspective of the users. This study, in an effort to inquire into the 'BIT' utilization factor and its vitalization plan, conducted a face to face survey of 172 citizens who had the experience in the 'BIT'. The result of the data analysis showed that usability, convenience, and availability were the critical factors for a BIT use. In addition, the general intention to use 'BIT' was found to be very high as much as 90.7%. The contributions of this study are as follows. The academic contributions is that it proved the relationship between usability, convenience and the intention to use suggested by the information technology acceptance model is supported even in case of 'BIT.' For the practitioners this study provides ground data for a local government to make a plan of a BIT extension.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.46-51
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• 2010

We propose the novel Hybrid bus arbitration policy that prevents a priority monopolization presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitrations. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and area overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others and effectively controls the bus utilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.88-97
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• 1990

In this paper, DPA bus is proposed for implementation of MC 68000 based tightly-coupled multiprocessor system. The DPMC and arbiter are designed that the local memory of each PE can accept memory request both from a local processor and from the system bus. The performance of the proposed system bus is evaluated by Stochastic Petri Net(SPN) system modeling. The processing power, the efficiency, and the utilization of system bus are simulated for various load factors.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.6D
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• pp.791-799
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• 2008

To build the system which has high utilization and usefulness for users, it is necessary to know the information type and use-demand that the use want. The purpose of this study is to forecast the preference and demand of utilization for bus information when bus information is offered through cellular phon. The accomplishments of this research are as follow : Firstly, importance on the level of individual factor and the value of change's figure can be evaluated, using preference analysis on bus information by conjoint analysis. Secondly, by establishing the use-demand model bus information using binary logit model, influence factor on whether or not the use of the user. Finally, ordered probit model was built by use behavior model in payment per call or per month of potential user of bus information. Through call times and sensitive analysis by payment methods, elasticity point, optimal payment fee, and use probability was analyzed. This study make application as basic to efficient bus information policy and to improve use rate of bus information in future because this study make it possible to get preference analysis, use-demand analysis and estimation of optimal payment fee which is reflecting various requirement in use of bus information user.

• Journal of Korean Society of Transportation
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• v.29 no.5
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• pp.43-54
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• 2011

After implementing "Semi-public management system of intra-city bus", the burden of financial aid for unprofitable routes is on the increase in Busan metro city. It becomes a heavy burden on the local finance, which needs to be resolved for improving the intra-bus system. The rainfall is one of the factors influencing the demands for intra-bus in urban transportation. Motivated by this fact, this study investigates the impact of rainfall on the intra-city bus demand. Actual bus users are surveyed on their patterns and recognition of using the bus according to the amount of rainfall. A rainfall forecast model using ordered probit model is presented, and the elasticity of the intra-city bus utilization to the amount of rainfall is also analyzed. The resulting findings could be applied to promote the use of intra-city buses and also be utilized as basic data for other studies to improve the intra-city bus system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.57-68
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• 1993

In this paper, we describe a multiprocessor system using the HiPi bus with pended protocol and multiple cache memories, and evalute the performance of the multiprocessor system in terms of processor utilization for various cache coherence protocols. The HiPi bus is delveloped as the shared bus of TICOM II which is a main computer system to establish a nation-wide computing network in ETRI. The HiPi bus has high data transfer rate, but it doesn't allow cache-to-cache transfer. In order to evaluate the effect of cache-to-cache transfer upon the performance of system and to choose a best-performed protocol for HiPi bus, we simulate as follows: First, we analyze the performance of multiprocessor system with HiPi bus in terms of processor utilizatIOn through simulation. Each of cache coherence protocol is described by state transition diagram, and then the probability of each state is calculated by Markov steady state. The calculated probability of each state is used as input parameters of simulation, and modeling and simulation are implemented and performed by using SLAM II graphic symbols and language. Second, we propose the HiPi bus which supports cache-to-cache transfer, and analyze the performance of multiprocessor system with proposed HiPi bus in terms of processor utilization through simulation. Considered cache coherence protocols for the simulation are Write-through, Write-once, Berkely, Synapse, Illinois, Firefly, and Dragon.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1741-1746
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• 2022

As the use of school buses becomes more common, related laws are being enacted, such as making it mandatory for children to check school bus dropouts due to frequent accidents caused by the negligence of school bus drivers and their guardians. In this paper, we propose a safe school bus system that links efficient radio-frequency identification (RFID) and mobile APP in terms of energy utilization and cost. The school bus system uses RFID cards to check information on children boarding the school bus, and real-time SMS transmission allows parents to safely send their children to and from school. Instructors on the school bus can check their children's disembarkation information once more through APP, preventing various accidents that may occur to children left on the bus. Due to the automation of the school bus operation log, daycare center teachers can not only check the information on getting on and off, but also manage the information on the attendance and discharge of the students.