• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1282-1295
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• 1994

In this paper, a hierarchical cluster multiprocessor system based on a hierarchical bus system is proposed and its cache coherency protocol is designed and implemented. The hierarchical cluster architecture aims at elimination the system bottleneck of the existing single bus system by adding a hierarchy of buses as the number of clusters is increased. Therefore the system is easy to scale up to a large number of processors. The proposed cache protocol is designed to be adapted to the general N-level (N>2) hierarchical cluster architecture. The original pended protocol is extended to implement the cache protocol on the system bus and cache coherency operations for this protocol are explained.

• Journal of Information Technology Services
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• v.9 no.2
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• pp.179-192
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• 2010

In order to resolve the problems of traditional Enterprise Application Integration (EAI) for system integration and to establish flexible enterprise IT environments, Enterprise Service Bus(ESB) which have distributed architecture and support Service Oriented Architecture(SOA) has introduced. Particularly, JBI which developed by the Java Community Process is most widely used to implement ESB for advantages of Java technology. In ESB based on JBI, reliable message delivery is very important to ensure stability of services and systems because it is a message driven architecture. But, it is difficult to verify messages and trace messages when system fault or service error occurred because JBI specification is not enough to address them. In this paper we has proposed the Message Monitoring Framework for JBI-based ESBs which for using in monitoring messages efficiently. It provides foundations for gathering and tracing message-related information about component installation, message exchange, service deploy by using proxy-based change tracking and delegation mechanism for data processing. The proxy which used in our solutions collects data about message automatically when it changed, and the delegation mechanism provides users flexibility for data processing. Also, we describe the performance evaluation results of our solution which is acceptable. We expect to it enables users to ensure reliability and stability of the JBI-based ESB by systematic monitoring and managing messages being used to interact among components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• ETRI Journal
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• v.38 no.6
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• Journal of Power Electronics
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• v.9 no.3
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• pp.447-455
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• 2009

The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.

• Proceedings of the KSR Conference
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• 2003.10b
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• pp.58-63
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• 2003

This study shows the functional contribution into the public transportation system for congestion area. And there is a introduction for the rapid bus transit developed in Europe community. It can be classified the public transportation as urban transit, subway and bus. For a few years, it has been introduced the AGT system as a role of the alternative and lengthening system of subway line. Recently, there is going on construction of AGT system in some regional cities. The AGT system has advantages in terms of accessibility and cost-effective rather than subway. But the bus system is advantageous at the points rather than AGT system. It is obvious that the bus system is most cost-effective for infrastructure and system rather than any other public transports. If the bus system has punctuality and precise docking, that becomes best choice for public transportation scheme. There are tries to develop new systems by means of the f1les up the advantages in bus and AGT system, which can be classified as BRT(Bus Rapid Transit}. The idea is simple; 'Thirik rail, use advanced buses.' It is introduced the IRISBUS system at this article, which was developed in Europe community. And it is introduced the project architecture to develop the similar system to IRISBUS in KRRI through National Transportation Key Technology R&D Project

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.9-24
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• 1999

We describe a heterogeneous simulation framework, so called DEVS-HLA, in which conventional simulation models and the DEVS (Discrete Event System Specification) models are interoperable. DEVS-HLA conceptually consists of three layers: model layer, DEVS BUS layer, and HLA (High Level Architecture) layer. The model layer has a collection of heterogeneous simulation models, such as DEVS, CSIM, SLAM, and so on, to represent various aspects of a complex system. The DEVS BUS layer provides a virtual software bus, DEVS BUS, so that such simulation models can communicate with each other. Finally, the HLA layer is employed as a communication infrastructure, which supports several good features for distributed simulation. The DEVS BUS has been implemented on the HLA/RTI (Run-Time Infrastructure) and a simple example of a flexible manufacturing system has been developed to validate the DEVS-HLA.

• KIEAE Journal
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• v.3 no.4
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• pp.33-36
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• 2003

Bus station is a public space which many people use and various activities are occurred in urban life. Main activities are waiting for departure or passengers with the feelings of joys and sorrows. Also sound information including announcing message of arrival and departure are to be considered carefully. Considering these roles of bus station, creating acoustic amenity is a prerequisite to the spaces. In this study, the spaces of bus station were classified into 4 spaces such as approaching path, waiting palace, departure and arrival platform. Observation survey was conducted to extract various activities in the view point of sound in each space. And subjective response was analyzed before and after introducing prepared sounds.