• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.54-60
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• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.

• Journal of the Korean Electrochemical Society
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• v.15 no.3
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• pp.165-171
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• 2012

Here is implemented MATLAB program to analyze the characteristic curves of cyclic voltammetry which involves the multi-electron electrode reaction considered as key processes in electrochemical systems. For the electrochemical mass-transfer system, Fick's concentration equation subject to semi-infinite diffusion model for the boundary condition was discretized and solved by the explicit finite difference method. The resulting concentration values were converted into currents at each node by using Butler-Volmer equation. Based on the good agreement between the present numerical solution and the existing experimental results, effects of kinetic constants and CV scan rates on the reaction mechanism in multi-electron transfer processes were investigated effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.18-24
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• 2011

A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.746-753
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• 2001

GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.

• Journal of the Optical Society of Korea
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• v.16 no.2
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• pp.133-140
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• 2012

In this study we investigate the use of 2D and 3D scanning optical coherence tomography (OCT) technology for use in apple blotch diagnosis. In order to test the possible application of OCT as a detection tool for apple trees affected by Marssonina coronaria, we conducted several experiments and compared the results from both healthy and infected leaves. Using OCT, we found several distinctive features in the subsurface boundary regions of both the diseased and healthy leaves. Our results indicate that leaves from diseased trees, while still appearing healthy, can be affected by M. coronaria. The A-scan analysis method confirmed that the boundaries found under the subsurface layers can be faint. This shows that M. coronaria can exert its influence on entire apple trees (as opposed to only on leaves with lesions) once it infects healthy trees. Our results indicate that OCT can be used as a noninvasive tool for the diagnosis of fungal disease in apple trees. Microscopic imaging results, performed as a histological study for comparison, correlated well with the OCT results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.14-19
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• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2004.04a
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• pp.210-213
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• 2004

We study the fracture behavior of the lumbar No.4 and No.5 vertebra subjected to posteroanterior (PA) forces, a three dimensional finite element method (FEM). The lumbar spine was modeled 3-dimensionally using commercial software based on the principle of convert stacked two dimensional CT scan images into three dimensional shapes. Determination of the boundary conditions corresponding to actual surgical conditions was not easy, so that the simplified spine beam analyses were performed. The results were used in three dimensional finite element (FE) analysis. This FE analysis, indicates that the fracture loads of the lumbar No.4 and No.5 vertebra are respectively 1550 N and 1500 N. These fracture loads are for static loading, but in actual conditions the load on the lumbar spine varies dynamically. We found that the fracture load of lumbar No.4 vertebra is larger than that of lumbar No.5 vertebra, as a result of the total stress difference by the moment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.85-92
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• 2004

A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.

• Korean Journal of Computational Design and Engineering
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• v.11 no.5
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• pp.335-343
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• 2006

Design changes for an original surface model are frequently required in a manufacturing area: for example, when the physical parts are modified or when the parts are partially manufactured from analogous shapes. In this case, an efficient 3D model updating method by locally adding scan data for the modified area is highly desirable. For this purpose, this paper presents a new procedure to update an initial model that is composed of combinatorial triangular facets based on a set of locally added point data. The initial surface model is first created from the initial point set by Tight Cocone, which is a water-tight surface reconstructor; and then the point cloud data for the updates is locally added onto the initial model maintaining the same coordinate system. In order to update the initial model, the special region on the initial surface that needs to be updated is recognized through the detection of the overlapping area between the initial model and the boundary of the newly added point cloud. After that, the initial surface model is eventually updated to the final output by replacing the recognized region with the newly added point cloud. The proposed method has been implemented and tested with several examples. This algorithm will be practically useful to modify the surface model with physical part changes and free-form surface design.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1619-1622
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• 2002

최근에 생산되는 디지털 VLSI칩들은 그 집적도가 계속 높아지고 있으며, 이러한 칩들을 장착한 보드의 경우도 그 복잡성이 점차 높아지고 있다. 이에 따라 칩 및 보드에 대한 철저한 테스트 과정이 요구된다. 지금까지 보드 테스트 방법으로 널리 쓰였던 ICT(In-Circuit Test)는 칩의 고집적화에 따른 핀 간격의 조밀화와 SMT(Surface Mount Technology), BGA(Ball Grid Array), MCM(Multi Chip Module) 등의 새로운 패키징 방식의 등장에 따라 테스트 방법으로의 한계성을 드러내고 있다. 이에 대한 대안으로 등장한 IEEE Std 1149.1 은 ICT의 한계성을 극복할 수 있는 기술일 뿐 아니라 여러 가지 장점을 가지고 있으며 그 활용 분야도 다양하다. 본 논문에서는 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생 가능한 고장들에 대한 고장 모델을 제시한다. 또한 각 고장 모델들의 양상과 진단 기법을 제시한다. 이를 통해 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생한 고장들을 검출할 수 있으며, 고장의 종류 및 성격, 그리고 고장의 발생 위치 등의 정보를 얻을 수 있다. IEEE Std 1149.1에 따른 보드 설계가 보드의 신뢰성 보장에 긴요함을 인식하는 계기가 되기를 기대하며 제시된 고장 모델 및 진단 기법이 기술적으로 중요한 참고자료가 되기를 기대한다.