• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.35-38
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• 2005

Treatise that see designed MDS block newly algorithm itself is concise and improve the speed of Twofish cryptographic algorithm that easy of implement is good but the processing speed has slow shortcoming than Rijndael cryptographic algorithm Problem of speed decline by a bottle-neck phenomenon of processing process existed as block that designed MDS block occupies critical path of Twofish cryptographic system Multiplication arithmetic that is used by operator in this MDS convex using LUT arithmetic and modulo-2 arithmetic speed decline and a bottle-neck phenomenon about MDS itself remove. Twofish cryptographic system including MDS block designed newly by these result confirmed that bing elevation of the processing speed about $10\%$ than existing Twofish cryptographic system.

• Journal of IKEEE
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• v.6 no.2 s.11
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• pp.152-160
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• 2002

This paper is the realization of the face recognition system for multimedia application. This system is focused on the design concerning the improvement of recognition rate and the reduction of processing time for face recognition. The non-modificated application of typical RGB color system enables the reduction of time required for color system transform. The neural network and the application of algorithm using face characteristic improves the recognition rate. After mosaicking an image, a face-color block has been selected through the color analysis of mosaic block. The characteristic of the face removes the mis-checked face-color candidate block. Finally, from the face color block, four special values are obtained. These values are processed to the neural network using the back propagation algorithm. The output values are the touchstone to decide the genuineness of face field. The realized system showed 90% of face recognition rate with less than 0.1 second of processing time. This result can be understood as sufficient processing time and recognition rate to find out the face block for multimedia application in dynamic image.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.51-61
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• 2008

This paper suggests a new way to implement high speed AES on Intel Core2 processors and AMD Athlon64 processors, which are used all over the world today. First, Core2 Processors of EM64T architecture's memory-access-instruction processing efficiency are lower than calculus-instruction processing efficiency. So, previous AES implementation techniques, which had a high rate of memory-access-instruction, could cause memory-bottleneck. To improve this problem we present the partial round key techniques that reduce the rate of memory-access-instruction. The result in Intel Core2Duo 3.0 Ghz Processors show 185 cycles/block and 2.0 Gbps's throughputs in ECB mode. This is 35 cycles/block faster than bernstein software, which is known for being the fastest way. On the other side, in AMD64 processors of AMD64 architecture, by removing bottlenecks that occur in decoding processing we could improve the speed, with the result that the Athlon64 processor reached 170 cycles/block. The result that we present is the same performance of Matsui's unpublished software.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.87-92
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• 2020

Although GPGPU (General-Purpose GPU) can maximize performance by parallelizing a task with tens of thousands of threads, those threads are internally grouped into a thread block, which is a base unit for processing and resource allocation. A thread block scheduler is a specialized hardware gadget whose role is to allocate thread blocks to GPGPU processing hardware in a round-robin manner. However, round-robin is a sequential allocation policy and is not optimized for GPGPU resource utilization. In this paper, we propose a thread block scheduler model which can analyze and quantify performances for various thread block scheduling policies. Experiment results from the implemented simulator of our model show that the legacy hardware thread block scheduling does not behave well when workload becomes heavy.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.417-424
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• 2019

This paper presents the design of a JPEG-LS codec for lossless image compression from AR/VR device. The proposed JPEG-LS(: LosSless) codec is mainly composed of a context modeling block, a context update block, a pixel prediction block, a prediction error coding block, a data packetizer block, and a memory block. All operations are organized in a fully pipelined architecture for real time image processing and the LOCO-I compression algorithm using improved 2D approach to compliant with the SBT coding. Compared with a similar study in JPEG-LS, the Block-RAM size of proposed STB-FLC architecture is reduced to 1/3 compact and the parallel design of the predication block could improved the processing speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.399-404
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• 2006

A real-time system is used for various systems from small embedded systems to distributed enterprise systems. Because it has a characteristic that provides a service on time, developers should make efforts to keep this property about time when developing real-time applications. As the result of research about real-time system indicates, TMO model supports various functions for time processing according to the real-time concept. And it guarantees response time which developers defined. So developers need a point of reference to define deadline and check the correctness of time. This paper proposes an improved PS-Block as an infrastructure of analysis tools for TMO to present a point of reference. There is a problem that the existing PS-Block has overhead caused by a policy making duplicated blocks. As such, this paper implements a PS-Block Timing Model to reduce the overhead due to block duplication, and defines a base class for searching in PS-Block. The PS-Block Timing Model, using an improved PS-Block structure, offers a point of reference of deadline and an infrastructure of execution time analysis according to the PS-Block configuration policy. Therefore, TMO developers can easily verify deadline of real-time methods, and improve reliability, and reduce development terms.

• Journal of electromagnetic engineering and science
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• v.6 no.4
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• pp.244-252
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• 2006

A block Jacket transform and. its block inverse Jacket transformn have recently been reported in the paper 'Fast block inverse Jacket transform'. But the multiplication of the block Jacket transform and the corresponding block inverse Jacket transform is not equal to the identity transform, which does not conform to the mathematical rule. In this paper, new binary block Jacket transforms and the corresponding binary block inverse Jacket transforms of orders $N=2^k,\;3^k\;and\;5^k$ for integer values k are proposed and the mathematical proofs are also presented. With the aid of the Kronecker product of the lower order Jacket matrix and the identity matrix, the fast algorithms for realizing these transforms are obtained. Due to the simple inverse, fast algorithm and prime based $P^k$ order of proposed binary block inverse Jacket transform, it can be applied in communications such as space time block code design, signal processing, LDPC coding and information theory. Application of circular permutation matrix(CPM) binary low density quasi block Jacket matrix is also introduced in this paper which is useful in coding theory.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.1048-1056
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• 1998

In this paper, a fractal image coding based on discrete wavelet transform is proposed to improve PSNR at low bit rates and reduce computational complexity of encoding process. The proposed method takes the absolute value of discrete wavelet transform coefficients, and then constructs significant coefficients trees, which indicate the positions and signs of the significant coefficients. This method improves PSNR and reduces computational complexity of mapping contracted domain pool onto range block, by matching only the significant coefficients of range block to coefficients of contracted domain block. Also, this paper proposes a classification scheme which minimizes the number of contracted domain blocks compared with range block. This scheme significantly reduces the number of range and contracted domain block comparison.

• Journal of the Society of Naval Architects of Korea
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• v.53 no.4
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• pp.275-281
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• 2016

One of the most important things for quality to meet ship-production schedule is an accuracy control. A ship is assembled by welding through whole production process, so it is important that loss by correction will not happen as much as possible by using some engineering skills like reverse design, reverse setting and margin for thermal shrinkage. These efforts are a quite effective in fabrication stages, but not in erection stages. If a ship block which consists of common steel is exposed to directional solar radiation, its dimensional accuracy will change high as time by its thermal expansion coefficient. Therefore, the measuring work would be often done at dawn or evening even with having a very accurate device. In this study, an FE analysis method is developed to solve this problem. It can change measured data affected by solar thermal distortion to ones not, even though ship-block is measured at an arbitrary time. It will use the time when measuring, the direction of block and the weather record by satellites. It is confirmed by a comparison between measured data of a ship-block and the result by suggested analysis method. Furthermore, a pre-processing system is also developed for fast application of the suggested analysis method.