• 대한산업공학회지
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• 제23권2호
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• pp.359-370
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• 1997

We consider a facility layout problem with the objective of minimizing total transportation distance, which is the sum of rectilinear distances between facilities weighted by the frequency of trips between the facilities. It is assumed that facilities are required to have rectangular shapes and there is no empty space between the facilities in the layout. In this study, a graph theoretic heuristic is developed for the problem. In the heuristic, planar graphs are constructed to represent adjacencies between the facilities and then the graphs are converted to block layouts on a continual plane using a layout construction module. (Therefore, each graph corresponds to a layout.) An initial layout is obtained by constructing a maximal weighted planar graph and then the layout is improved by changing the planar graph. A simulated annealing algorithm is used to find a planar graph which gives the best layout. To show the performance of the proposed heuristic, computational experiments are done on randomly generated test problems and results are reported.

• 한국전자통신학회논문지
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• 제15권1호
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• pp.61-70
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• 2020

본 연구에서는 근무자의 주관적인 판단으로 이루어지는 기존의 좌석배치 방법을 보완하고 근무효율성을 높이기 위한 IOT 기반 데스크 배치 방안을 제안하였다. 경량화 된 사물 인터넷 시스템을 근무장 데스크 배치에 도입하여 근무자 좌석 배치 추천을 합리적으로 보조하기 위하여 데스크의 업무상태를 알아내기 위한 센서의 기능과 종류와 네트워크 프로토콜을 결정하였고 데스크 배치를 위한 근무형태 인지 자료 수집 방법을 제안하였다. 획득한 데이터를 이용하여 좌석배치 추천방안을 결정 할 때, Block Stacking에서 사용하는 알고리즘을 활용하였다. 그 결과 사물인터넷 환경에서 합리적인 데스크 배치를 위한 산술적 근거를 제시할 수 있었으며, 향후 근무자들의 선호도에 더하여 근무형태를 근거로 하는 진보된 유연 좌석제에 적용할 수 있음을 보였다.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1056-1067
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• 1987

This paper presents a design procedure for building block integrated circuits that is based on the digraph relaxation model. A set of optimization procedure is prosented for a minimum area and routing-fecsible placement of IC building blocks. Chip area optimization is subject to perimeter and area constraints on the component rectangles in the dissection.

• 융합신호처리학회논문지
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• 제4권4호
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• pp.81-86
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• 2003

최근 VLSI 회로 설계는 자동 레이아웃(automatic layout) 툴을 사용하여 효과적으로 이루어지고 있다. 자동 레이아웃은 VLSI 칩 상에 모듈들의 위치를 결정하는 배치와 각 모듈간을 상호 연결하는 배선 두 가지의 중요한 기능으로 구성되어 있다. VLSI 칩의 성능과 면적은 이 두 가지의 기능을 수행하는 알고리즘의 성능에 따라 크게 좌우된다. 스위치박스 배선은 VLSI 설계 과정중의 하나로, 채널 배선과는 다르게 4면에 존재하는 같은 네트에 속하는 터미널들을 배선하는 문제이며, 모든 터미널들을 완전히 연결을 해야 하는 문제이다. 본 논문에서는 스위치박스 배선 문제에 대하여 유전자 알고리즘(genetic algorithm; GA)을 이용한 해 공간 탐색(solution space search) 방식을 제안하였으며, 제안한 방식을 여러 문제들에 대해 기존의 스위치박스 배선 알고리즘과 비교, 분석한 결과 거의 대부분의 문제들에서 배선 길이와 비아수 측면에서 더 좋은 결과를 얻을 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1539-1542
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• 2002

In layout of LSI and PWB, block pack- ing problem is very important in order to reduce chip area. Sequence-pair is typical one of conventional pack- ing method and can search nearly-optimal solution by using Simulated Annealing(SA). SA takes huge computation time due to evaluating of various packing results. Therefore, Sequence-pair is not effective enough for fast layout evaluation including estimation of wire length and rotation of every blocks. This paper proposes an efficient block packing method to minimize wire length and chip area. Our method searches an optimal packing efficient- ly by using a cluster growth algorithm with changing the most valuable packing score on packing process.

• 한국주거학회논문집
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• 제22권1호
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• pp.35-42
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• 2011

The objective of this study is to investigate the functional conformity based on the analysis of the spatial connectivity of block housing using space syntax. Three cases were selected which have important meanings in 1920s. The properties of spatial configuration were derived from an urban-context approach and without urban context analysis, and spatial connectivity and functional conformity were analyzed using references. The results of the study revealed that the arrangement of block housing were different from one another notwithstanding their similar layout characteristics. The relationships between urban streets and housing complexes were identified, and the public spaces were being arranged as semi-public spaces, whereas blocks as private spaces by separating functions. This study provides the implications for the planning of low rise-high density housings by means of analyzing the spatial connectivity of the spatial layout characteristics of European block housing, recognizing the relationships between urban communities and housing complexes.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• 대한산업공학회지
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• 제38권1호
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• pp.7-16
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• 2012

Manufacturing system design poses many challenges for new factory construction. Factories producing the same product may nevertheless have different layouts. The machining line of the engine shop in an automotive factory is a typical flow line, but the layout concept of the line varies among factories. In this paper, a simulation study on the design concept of the manufacturing system for automotive engines is discussed. For comparison, three types of real engine block lines in different factories are analyzed, and three structures of parallel lines are extracted. The effects of failure distribution on the performance measures of three types of parallel line structures are investigated, and some insights are offered regarding the layout concept.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 추계학술대회 논문집
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• pp.334-338
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• 2000

One of the major drawbacks of the existing facility layout methods is that most of them were developed based on pre-defined cost functions, and therefore fail to cope with the dynamic aspects of modern manufacturing systems. Another drawback is that due to the poor representation capability of the block diagrams, they are not able to convey the sufficient information needed by facility designers. In this paper, a system for solving facility layout problem considering these matters in cellular manufacturing environment is proposed and implemented using GA approach with embedded simulation module and virtual reality technologies.

• International Journal of Contents
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• 제1권2호
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• pp.5-9
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• 2005

Currently most Internet documents including data are made based on predefined templates, but templates are usually formed only for main data and are not helpful for information retrieval against indexes, advertisements, header data etc. Templates in such forms are not appropriate when Internet documents are used as data for information retrieval. In order to process Internet documents in various areas of information retrieval, it is necessary to detect additional information such as advertisements and page indexes. Thus this study proposes a method of detecting the layout of Web pages by identifying the characteristics and structure of block tags that affect the layout of Web pages and calculating distances between Web pages. This method is purposed to reduce the cost of Web document automatic processing and improve processing efficiency by providing information about the structure of Web pages using templates through applying the method to information retrieval such as data extraction.