• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.324-330
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• 2004

In this paper, we propose the TCM(Trellis coded modulation) decoding scheme that reduces the number of operations in branch metric with STBC(space time block codes) channel information and present the implementation results. The proposed TCM decoding scheme needs only 1 signal point in each TCM subset. Using bias point scheme, It detects the minimum distance symbol. The proposed TCM decoding scheme can reduce the branch metric calculations. In case of 16QAM 8 subset, the reduction ratio is about 50％ and for 64QAM 8 subset, about 80％ reduction can be obtained. The results of logic synthesis for the TCM and STBC decoder with the proposed scheme are 57.6K gate count.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.48-55
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• 2012

Because of increasing complexity in maximum-likelihood (ML) decoding of four of higher antenna scenario, Partial Interference Cancellation (PIC) group decoding could be the perfect solution to reduce the decoding complexity occurs in ML decoding. In this paper, we separate the symbols the users in the layered basis and find the equivalent channel matrix. Based on the equivalent channel matrix we provide the grouping scheme. In our paper, we construct a block wise transmission technique which will achieve the desired code rate and reduce the complexity and provide less transmission time. Finally we show the different grouping performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.907-914
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• 1997

The conventional decoding procedure for the images encoded using fractal contractive transformation algorithms is performed by applying the transformations iteratively for an arbirary initial image. In this paper, we showed that the atractor image can be obtained analytically when the image is encoded using the fractal algorithm proposed by Monro and Dudbridge, in which the corresponding domain block for a range block is fixed. Using the analytical formula, we can obtain the attractor image without iteration procedure. Computer simulation results for various test images show that we can increase the image decoding speed by more than five times when we use the analytical formula compared to the previous iteration methods. Also we confirmed that the real time decoding by software on PD is possible for the moving picture with QCIF formats.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1062-1067
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• 2008

ABBA codes, a class of quasi-orthognal space-time block codes (QoSTBC) proposed by Tirkkonen and others, allow full rate and a fast maximum likelihood (ML) decoding, but do not have full diversity. In this paper, a linear complex precoder is proposed for ABBA codes to achieve full rate and full diversity. Moreover, the same diversity produce as that of orthogonal space-time block code with linear complex precoder (OSTBC-LCP) is achieved. Meanwhile, the size of the linear complex precoder can be reduced by half without affecting performance, which means the same complexity of decoding as that of the conventional ABBA code is guaranteed.

• Journal of Communications and Networks
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• v.9 no.1
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• pp.1-10
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• 2007

This paper proposes a multimodal generalized Gaussian distribution (MGGD) to effectively model the varying statistical properties of the extrinsic information. A subsidiary maximum likelihood decoding (MLD) algorithm is subsequently developed to dynamically select the most suitable MGGD parameters to be used in the component maximum a posteriori (MAP) decoders at each decoding iteration to derive the more reliable metrics performance enhancement. Simulation results show that, for a wide range of block lengths, the proposed approach can enhance the overall turbo decoding performance for both parallel and serially concatenated codes in additive white Gaussian noise (AWGN), Rician, and Rayleigh fading channels.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.4
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• pp.223-228
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• 2014

It is known that a belief propagation algorithm is a fast decoding scheme for LT codes but it require a large overhead, especially for a short block length LT codes. In this paper an improved belief decoding algorithm using searching method for degree-1 packets is proposed for a small overhead. The proposed decoding scheme shows the desirable performance in terms of overhead while guaranteeing the same computational complexity with respect to the conventional BP decoding scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.36-44
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• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.798-801
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• 2010

This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.