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Design of Viterbi Decoders Using a Modified Register Exchange Method  

이찬호 (숭실대학교 정보통신전자공학부)
노승효 (삼성전자 시스템 LSI 사업부 LSI 개발 1팀)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.1, 2003 , pp. 36-44 More about this Journal
Abstract
This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.
Keywords
Viterbi decoder; register exchange; traceback; VLSI; block decoding; TCM;
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