• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.196-200
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• 1987

In this paper A NET-CUE System is designed and implemented for tramsmission of the network cuing informations with using data packet broad casting techniques. This system is composed with encoder and decoder. To show the performance of this system An eye height and bit error rate are cheched. The eye height is greater than 74% and The bit error rate is less than 4.6 * 10 The exper imental results show that this system provides a good quality of the operation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.537-540
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• 2004

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation. we present an Interpolation type architecture. In order to overcome the problems of high speed operation further a novel encoder, a circuit for the Reference Fluctuation, an Averaging Resistor and a Track & Hold for the improved SNR are proposed. The proposed Interpolation ADC consists of Track & Holt four resistive ladders with 64 taps, 32 comparators and digital blocks. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.605-614
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• 1992

초기단계의 제품 검사방법은 단순히 제품이 제대로의 기능을 수행하는지 안하는지에 대해서만 검사하고 결정을 내릴 뿐이었다. 대부분의 검사란, 검사자에게 최종적으로 제품이 인수된 후에 제품의 상태여부를 한정적이고, 제한적으로만 판단하여 검사결과를 제공하여왔다. 현대의 제품특성이 구조적 복잡성의 증가, 제품불량 현상파악의 난이도 증가등으로 제품의 사용절차, 검사, 유지보수, 부품교환등이 점점 더 난해해지고, 검사자의 개인적인 숙련도도 증가하게 되어, 제품을 유지보수하는데 더 많은 비용과 시간을 필요로하게 되었다. 이러한 문제들의 해결방안의 하나로 제품의 자체에 스스로 검사할 수 있는 체계적인 시스템을 설치하게 되어 BIT(Built-In-Test)가 탄생하게 되었다. BIT는 현존하는 제품뿐만아니라, 생산될 제품의 설계단계에서도 많이 응용되어 제품의 RAM(Reliability, Availability, Maintainability)에 많은 기여를 해왔다. 이 PAPER는 지금까지 BIT가 주로 Military System에 적용되어온 것을 Commercial system으로의 변환을 위한 기초작업을 제시하고 여러 대안을 열거하였으며, BIT가 갖고 있는 문제점들을 파악하여, 향후 고도화 되가는 산업사회의 요구에 부응할 수 있는 토대를 마련코자 Survey하였다.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.199-202
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• 2003

In this paper, we propose a new 3D coding method for heterogeneous systems over enhanced Access Grid (e-AG) with 3D display using spatio-temporal scalability. The proposed encoder produces four bit-streams: one base layer and enhancement layer l, 2 and 3. The base layer represents a video sequence for left eye with lower spatial resolution. An enhancement layer l provides additional bit-stream needed for reproduction of frames produced in base layer with full resolution. Similarly, the enhancement layer 2 represents a video sequence for right eye with lower spatial resolution and an enhancement layer 3 provides additional bit-stream needed for reproduction of its reference pictures with full resolution. In this system, temporal resolution reduction is obtained by dropping B-frames in the receiver according to network condition. The receiver system can select the spatial and temporal resolution of video sequence with its display condition by properly combining bit-streams.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.675-676
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• 2012

In this paper, we are implemented the signal measurement system based on FPGA. The proposed hardware was mapped into Cyclone III from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1532-1539
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digial loop filter is combined with an error symbol detecting circuit using an adaptive window. Suppressing the tracking process when hop mute and impulse noises are detected improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. The simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.55-61
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• 2003

The Data Encryption Standard(DES) has been a worldwide standard for over 20 years. DES is one of the block encryption techniques which ciphers 64-bit input data blocks using a 56-bit private key. The DES algorithm transforms 64-bit input in a series of steps into a 64-bit output. Thus, it is impossible to deduce the plaintext from the ciphertext which encrypted by this algorithm without the key. This paper presents an implementation of RFID roader system using the DES algorithm. An implemented system enhances the credibility of the encryption algorithm by using the Cipher Block Chining(CBC). Experimental results also show that the implemented system has better performance over the conventional commercial product.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.7
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• pp.1-8
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• 1997

In this paper, Stokes parameters which represent the states of polarization of transmitted light are determined by potential function, which is used to obtain signals points in a multidimensional Euclidean structure. And performance of multilevel polarization shift keying(POLSK) system using the obtained parameters is also represented and analyzed. As results, bit error rate of multilevel POLSK system using the potential function is shown to be lower than the conventional one using the distance matrix. And as number of levels increases, the number of photons per bit for bit error rate of 10$^{-9}$ is also increased linearly. The multilevel POLSK system, therefore, is an energy efficient modulation technque as compared with the convnetional ones.