• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1391-1394
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• 1997

This paper proposes a new image processing algorithm to recognize korean documents. It take out the region of text area form input image, then it makes esgmentation of lines, words and characters in the text. A precision segmentation is very important to recognize the input document. The input image has 8-bit gray scaled resolution. Not only the histogram but also brightness dispersion graph are used for segmentation. The result shows a higher accuracy of document recognition.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.427-430
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• 1995

This paper proposes a new image processing algorithm to recognize korean documents. It take out the region of syllable area from input character image, then it makes recognition of a consonant and a vowel in the character. A precision segmentation is very important to recognize the input character. The input image has 8-bit gray scaled resolution. Not only the shape but also vertical and horizontal lines dispersion graph are used for segmentation. Theresult shows a higher accuracy of character segmentation.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.04a
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• pp.694-695
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• 2013

An experimental study has been made with the use of time reversal concepts to recover the input waveform in a long range propagation of dispersive Lamb waves. Three techniques have been tested: Regular TR, 1 bit TR and Inverse filter (IF). The IF approach was found to completely recover the original input signal. Moreover, the IF technique significantly increases the contrast, i.e., the ratio of the recovered signal and the sideband signal.

• Journal of Biomedical Engineering Research
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• v.12 no.3
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• pp.191-202
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• 1991

This paper describes ECG data compression algorithm using neural network. As a learning method, we use back error propagation algorithm. ECG data compression is performed using learning ability of neural network. CSE database, which is sampled 12bit digitized at 500samp1e/sec, is selected as a input signal. In order to reduce unit number of input layer, we modify sampling ratio 250samples/sec in QRS complex, 125samples/sec in P & T wave respectively. hs a input pattern of neural network, from 35 points backward to 45 points forward sample Points of R peak are used.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4A
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• pp.189-196
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• 2012

A WAVE(Wireless Access for Vehicular Environment) system is a vehicle communication technology. The system provides the services to prevent vehicle accidents that might occur during driving. Also, it is used to provide various services such as monitoring vehicle management and system failure. However, the scrambler bit operation of WAVE system becomes less efficient in the organizations of software and hardware design because the parallel processing is impossible. Although scrambler algorithm proposed in this paper has different processing speed depending on input data 8 bit, 16 bit, 32 bit, and 64 bit. it improves the processing speed of the operation because it can make parallel processing possible depending on the input unit.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.2
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• pp.123-129
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• 2002

5-bit broadband MMIC phase shifter has been designed and fabricated. For the broadband performance, 11.25$^{\circ}$, 22.5$^{\circ}$, 45$^{\circ}$ and 90$^{\circ}$ bit have been designed with Lange coupler and 180$^{\circ}$ bit has been implemented by using shorted coupled line with Lange coupler and $\pi$-network of transmission line. Due to Lange coupler with large size, the Lange couplers have been folded far circuit size reduction. Low loss PIN diode has been utilized as a switch for each bit. Fabricated 5-bit broadband phase shifter shows the measured results that RMS phase error of 5 major phases is 3.5$^{\circ}$, maximum insertion loss is 12.5 dB, and maximum input and output return loss are 7 dB and 10 dB, respectively. The size of fabricated phase shifter is 6.5$\times$5.3 $ extrm{mm}^2$.