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http://dx.doi.org/10.5573/ieie.2014.51.1.107

Reduced-bit transform based block matching algorithm via SAD  

Kim, Sang-Chul (TV R&D Center, LG Electronics)
Park, Soon-Yong (School of Computer Science and Engineering, Kyungpook National University)
Chien, Sung-Il (School of Electronics Engineering, Kyungpook National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.1, 2014 , pp. 107-115 More about this Journal
Abstract
The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.
Keywords
block matching algorithm; bit-plane matching; reduced-bit transform; SAD; combinational logic;
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