• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.12a
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• pp.620-624
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• 2003

In［5］, the bit security of keys obtained from protocols based on pairings has been discussed. However it was not able to give bit security of tripartite authenticated key(TAK) agreement protocol of type 4. This paper shows the bit security of keys obtained from TAK-4 protocol.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.392-393
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• 2019

본 논문에서는 전기 보트 추진을 위한 SPMSM(Surface mounted Permanent Magnet Synchronous Motor) 구동 시스템을 개발하였다. 전차원 폐루프 관측기를 이용하여 외란 토크 관측기를 구성하고, 관측된 외란 성분을 속도 제어기 출력에 보상하여 속도 제어 성능을 향상시켰다. 리튬이온 배터리, 인버터 및 1kW SPMSM으로 구성된 전기 보트 추진 시스템을 이용한 구동 실험을 통해 추진용 전동기의 속도 제어 특성을 확인하였다.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.384-385
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• 2019

본 논문에서는 단상 컨버터/3상 인버터 시스템에서 공통모드 전압 저감을 위한 PWM 기법을 제안한다. 컨버터/인버터 시스템은 스위칭에 의한 공통모드 전압으로 인해 전동기의 누설전류와 절연파괴 등의 문제가 발생할 수 있다. 이에 본 논문에서는 영전압벡터 인가시간에 따라 유효전압벡터의 위치를 선정하여 공통모드 전압을 저감하는 방법에 대해 제안한다. 모의실험을 통하여 제안된 기법의 효용성을 검증하였다.

• Journal of Korea Multimedia Society
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• v.8 no.7
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• pp.961-973
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• 2005

In this paper, we proposed an adaptive steganography of color image using bit-planes and multichannel characteristics. Applying fixing threshold, if we insert information into all bit-planes of RGB channel, each channels showed different image quality. Therefore, we first defined the channel weight and the bit-plane weight to solve the fixing threshold problem of BPCS (bit-plane complexity steganography) method. We then proposed a new adaptive threshold method using the bit-plane weight of channels and the bit-plane complexity of cover image to increase insertion capacity adaptively In the experiment, we inserted information into the color images with the same image quality and same insertion capacity, and we analyzed the Insertion capacity and image quality. As a result, the proposed method increased the insertion capacity and improved the image quality than BPCS method.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.647-656
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• 2011

Motion estimation using one-bit transform and two-bit transform reduces the complexity for computation of matching error; however, the peak signal-to-noise ratio (PSNR) is degraded. Modified 1BT (M1BT) and modified 2BT (M2BT) have been proposed to compensate degraded PSNR by adding conditional local search. However, these algorithms require many additional search points in fast moving sequences with a block size of $16{\times}16$. This paper provides more efficient search method by preparing candidate blocks using the number of non-matching points (NNMP) than the conditional local search. With this NNMP-based search, we can easily obtain candidate blocks with small NNMP and efficiently search final motion vector. Experimental results show that the proposed algorithm not only reduces computational complexity, but also improves PSNR on average compared with conventional search algorithm used in M1BT, M2BT and AM2BT.

• Journal of KIISE
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• v.43 no.6
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• pp.692-699
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• 2016

C compilers for 8-bit MCUs used in washing machines and refrigerators often do not follow the C standard to improve runtime performance. Developers who are unaware of the difference between C compilers following the C standard and the C compilers for 8-bit MCU can cause bugs that do not appear in the standard C environment but appear in the embedded systems using 8-bit MCUs. It is difficult for bug detectors that assume the standard C environment to detect such bugs. In this paper, we introduce integer promotion bugs caused by the different integer promotion rules of the C compilers for 8-bit MCU from the C standard and propose 5 bug patterns where the integer promotion bugs occur. We have developed an integer promotion bug detection tool and applied it to the washing machine control software developed by the LG electronics. The integer promotion bug detection tool successfully detected 27 integer promotion bugs in the washing machine control software.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.881-886
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• 2007

This study was to develope a vibrotactile display system using windows media player from digital audio signal. WMPlayer10SDK system which was plug-in tool by microsoft windows media player provided its video and audio signal information. The audio signal was tried to be change into vibrotactile display. Audio signal had 4 sections such as 8bit, 16bit, 24bit, and 32bit. Each section was computed its frequency and vibrato scale. And data was transferred to 38400bps network port(COM1) for vibration. Using this system was able to develop the music suit which presented tactile feeling of music beyond sound. Therefore, it may provide cross modal technology for fusion technology of human senses.