• 한국위성정보통신학회논문지
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• 제8권2호
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• pp.36-43
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• 2013

본 논문에서는 고전압에서 동작하는 DDIC(display driver IC) 칩의 정전기 보호소자로 사용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘이 분석되었다. 이온주입 조건을 달리하는 매트릭스 조합에 의한 수차례의 2차원 시뮬레이션 및 TLP 특성 데이타를 비교한 결과, BJT 트리거링 후에 더블 스냅백 현상이 나타났으나 웰(well) 및 드리프트(drift) 이온주입 조건을 적절히 조절함으로써 안정적인 ESD 보호성능을 얻을 수 있었다. 즉, 최적의 백그라운드 캐리어 밀도를 얻는 것이 고전압 동작용 정전기보호소자의 고전류 특성에 매우 중요한 영향을 주는 임계인자(critical factor)임을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1309-1310
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• 2007

본 논문에서는 IGBT 소자 중 온저항을 낮추고 집적성을 향상시키기 위해 고안된 트렌치 게이트 IGBT의 단점인 게이트 코너에서의 전계 집중현상을 완화하기 위해 P+ 베이스 영역에 트렌치 전극을 형성하고, 트렌치 바닥면에 P+ 층을 형성한 새로운 구조를 제안하고 TSUPREM과 MEDICI 시뮬레이션을 사용하여 전기적 특성을 분석하였다. 제안한 구조를 시뮬레이션한 결과 순방향 저지시에 15% 이상의 항복전압 향상을 보였으며, 이 때 온저항 특성과 문턱전압의 변화는 없었다. 전계 분포를 3차원적 시뮬레이션을 통해 트렌치 전극 바닥에 형성된 P+ 층에 의해 전계집중이 분산되는 전계분산 효과에 의해 항복전압을 향상시킴을 확인하였다. 전계분산 효과에 의한 항복전압향상은 트렌치 게이트의 코너와 트렌치 전극의 코너의 깊이가 같을수록 두 코너 사이의 거리가 가까울수록 커짐을 시뮬레이션을 통해 확인하였다. 제안 구조는 공정상 복잡성이 야기되지만 15%이상의 항복전압향상 효과는 소자 특성 개선에서 많은 응용이 기대된다.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• 한국전기전자재료학회논문지
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• 제32권5호
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• pp.366-370
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• 2019

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a $20^{\circ}C$ change in temperature from 1,000 to $1,160^{\circ}C$ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.

• 한국철도학회논문집
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• 제13권5호
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• pp.504-508
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• 2010

고전압 절연 게이트 바이폴라 트랜지스터 (IGBT)의 개발로 기존의 GTO(Gate Turnoff Thyristor)가 적용되는 분야에서 더 효율적인 새로운 소자로 인정받고 있다. IGBT는 금속 산화막 반도체 트랜지스터(MOSFET)와 바이폴라 전력 트랜지스터의 장점을 결합한 소자이다. IGBT의 전기적 특성의 변화는 주로 입력단자에 MOSFET와 출력단자에 PNP 트랜지스터의 특성에 달려있다. IGBT의 가장 중요한 설계변수중의 하나인 문턱전압의 변화는 방사선이 존재하는 환경에 게이트 산화막(oxide)에서 전하포획(charge trapping)에 의해 발생되고 에너지 손실을 야기시킨다. 또한, 에너지 손실은 초퍼회로의 인덕턴스 값이 변화될 때 발생됨을 연구한다. 본 논문에서 IGBT의 전기적 특성을 SPICE로 시뮬레이션하고, IGBT 기반 인덕턴스와 문턱전압의 변화에 따른 전기적 특성을 분석하고자 한다.

• ETRI Journal
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• 제37권6호
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.632-642
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• 2017

This paper presents an improved approach towards reducing the switching loss of insulated gate bipolar transistors (IGBTs) for a medium-capacity-class power conditioning system (PCS). In order to improve the switching performance, the switching operation is analyzed, and based on this analysis, an improved switching method that reduces the switching time and switching loss is proposed. Compared to a conventional gate drive scheme, the switching loss, switching time, and delay are improved in the proposed gate driving method. The performance of the proposed gate driving method is verified through several experiments.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 추계학술대회 논문집
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• pp.93-96
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• 1993

BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.158-162
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• 1995

We report rf and power characteristics of AlGaAs/GaAs Heterojunction Bipolar Transistor (HBTs) for X-band power applications. HBTs have been fabricated with polyimide a an interlayer dielectric. By characterizing the DC and RF characteristics we obtained the maximum current gain of 45, BV$\_$CEO/ of 10 V, fT of 30 GHz and f$\_$max/ of 17 GHz for device with 6x14$\mu\textrm{m}$$^2$emitter size. To extract accurate equivalent parameters, the De-embedded method was applied for extraction of parasitic parameters and the calculation of circuit equations for intrinsic parameters. Based on the Load-pull method, power characteristics was simulated and measured to get the maximum output power of the device.

• 전자공학회논문지A
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• 제30A권10호
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.