• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.64-72
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• 1998

In this paper, the design of a current integrator for low-voltage, low-power, and high frequency applications using complementary high swing cascode current-mirror is presented. The proposed integrator decreases output current errors due to non-zero input resistance and non-infinite output resistance of the simple current integrator. As a design example, the 3rd order Butterworth lowpass filter is designed by a leapfrog method. Also, we apply the predistortion design method to reduce the magnitude distortion which occurs at a cutoff frequency by the undesirable phase shift of a lossless current integrator. The designed current-mode filter is simulated and examined by SPICE using 0.8$\mu\textrm{m}$ CMOS n-well process parameters. The simulation results show 20MHz cutoff frequency and 615㎼ power dissipation with a 2V power supply. And the cutoff frequency of the filters can be easily changed by the DC bias current.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.219-225
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• 2013

Program and erase characteristics of the elliptic gate all around (e-GAA) SONOS cell have been studied as the variation of eccentricity of the channel. An analytic program and erase model for the elliptic GAA SONOS cell is proposed and evaluated. The model shows that the ISPP (incremental-step-pulse programming) property is changed non-linearly as the eccentricity of the e-GAA SONOS cell is increased. It is differently from the well known linear relationship for that of 2D SONOS and even 3D circular SONOS cell with program bias. We can find that the simulation results of ISPP characteristics are in accord with the experimental data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.84-92
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• 2000

A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.39-45
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• 1998

SrBi$_{2}$Ta$_{2}$O$_{9}$ (SBT) ferroelectric thin films for nonvolatile memory were prepared on Pt/Ti/SiO$_{2}$/Si and RuO$_{2}$/SiO$_{2}$/Si substrates by RF magnetron sputtering. The dependences of crystalline and electrical properties on the lower electrode type(Pt and RuO$_{2}$) and the annealing temperatures were investigated. SBT films regardless of their electrode types showed typeical Bi layered peroviskite crystal structures. The crystalline quality of as-deposited SBT films was improved by the rapid thermal annealing at 650.deg. C for 30 sec. The remanetn polarization of 2Pr (Pr+-Pr-) of the annealed SBT films deposited on Pt/Ti/SiO$_{2}$/Si substrates were about 11 .mu.C/cm$^{2}$ and 3 .mu.C/cm$^{2}$, respectively. The leakage currents at 3 V bias voltage were about 0.8 .mu.A/cm$^{2}$ for SBT/ Pt/Ti/SiO$_{2}$/Si and about 1 .mu.A/cm$^{2}$ for SBT/RuO$_{2}$/SiO$_{2}$/Si sample. SBT films annealed at 650 .deg. C showed no degradation in Pr values after 10$^{11}$ polarization switching cycles, indicating good fatigue properties. In addition, for SBT samples deposited on Pt/Ti/SiO$_{2}$/Si, Pr values increased to more than that of initial state, suggesting the increament of leakage current caused by repeated polarization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.698-701
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• 2013

This paper has presented the change of subthreshold swings for gate oxide thickness of asymmetric double gate(DG) MOSFET, and solved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET is three terminal device. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine the bias voltage and oxide thickness for top and bottom gates. As a result to observe the subthreshold swings for the change of top and bottom gate oxide thickness, we know the subthreshold swings are greatly changed for gate oxide thickness. Especially we know the subthreshold swings are increasing with the increase of top and bottom gate oxide thickness, and top gate oxide thickness greatly influences subthreshold swings.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.826-830
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• 2013

In this paper, we carried out the investigations of both etch characteristics and mechanisms for the $SnO_2$ thin films in $O_2/BCl_3/Ar$ plasma. The dry etching characteristics of the $SnO_2$ thin films was studied by varying the $O_2/BCl_3/Ar$ gas mixing ratio. We determined the optimized process conditions that were as follows: a RF power of 700 W, a DC-bias voltage of - 150 V, and a process pressure of 2 Pa. The maximum etch rate was 509.9 nm/min in $O_2/BCl_3/Ar$=(3:4:16 sccm) plasma. From XPS analysis, the etch mechanism of the $SnO_2$ thin films in the $O_2/BCl_3/Ar$ plasma can be identified as the ion-assisted chemical reaction while the role of ion bombardment includes the destruction of the metal-oxide bonds as well as the cleaning of the etched surface form the reaction products.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.80-86
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• 2010

This work has been measured and analyzed the device degradation of NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOS transistors of gate channel length 0.13 [${\mu}m$]. From the relation between the variation of threshold voltage and subthreshold slop by NBTI stress, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. As a results, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress parameters of nanoscale CMOS communication circuit design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.48-51
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• 2009

One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.

• Proceedings of the Korean Magnestics Society Conference
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• 2011.12a
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• pp.7-8
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• 2011

Although yttrium iron garnet (YIG) has provided a great vehicle for the study of spin waves in the past, associated difficulties in film deposition and device fabrication using YIG had limited the applicability of spin waves to practical devices. However, microfabrication techniques have made it possible to characterize both the resonant as well as the travelling characteristics of spin waves in permalloy (Py). A variety of methods have been used for measuring spin waves, including Brillouin light scattering (BLS), magneto-optic Kerr effect (MOKE), vector network analyzer ferromagnetic resonance (VNA-FMR), and pulse inductive microwave magnetometry (PIMM). PIMM is one of the most preferred methodologies of measuring travelling spin waves. In this method, an electrical impulse is applied at one of two coplanar waveguides patterned on top of oxide-insulated Py, producing a local disturbance in the magnetization of the Py. The resulting disturbance travels down the Py in the form of waves, and is inductively picked up by the other coplanar waveguide. We investigate the effect of the pulse width of excitation pulses on the generated spin wave packets using both experimental results and micromagnetic simulations. We show that spin wave packets generated from electrical pulses are a superposition of two separate spin wave packets, one generated from the rising edge and the other from the falling edge, which interfere either constructively or destructively with one another, depending upon the magnitude and direction of the field bias conditions. A method of spin wave amplitude modulation is also presented by the linear superposition of spin waves. We use interfering spin waves resulting from two closely spaced voltage impulses for the modulation of the magnitude of the resultant spin wave packets.