• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2311-2317
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• 2011

In this paper, we study the temperature change of a ${\mu}$-bolometer focal plane array with a capacitive transimpedance amplifier bias cancellation circuit. Thermal analysis is essential to understand the performance of a ${\mu}$-bolometer focal plane array, and to improve the temperature stability of a focal plane array characteristics. In this study, the thermal analyses of a ${\mu}$-bolometer and its two reference detectors are carried out as a function of time. The analyses are done with the $30{\mu}m$ pitch $320{\times}240$ focal plane array operating of 60 Hz frame rate and having a columnwise readout. From the results, the temperature increase of a ${\mu}$-bolometer in FPA by an incident IR is estimated as $0.689^{\circ}C$, while the temperature increase by a pulsed bias as $7.1^{\circ}C$, which is about 10 times larger than by IR. The temperature increase of a reference detector by a train of bias pulses may be increased much higher than that of an active ${\mu}$-bolometer. The suppression of temperature increase in a reference bolometer can be done by increasing the thermal conductivity of the reference bolometer, in which the selection of thermal conductivity also determines the range of CTIA output voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.8 s.99
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• pp.777-782
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• 2005

In this paper, adaptive bias circuit and PBG structure have been employed to suppress IMD(Inter-Modulation Distortion) and improve PAE(Power Added Efficiency) of the Doherty amplifier. Gate bias voltage has been controlled with the envelope of the input RF signal and PBG structure has been employed on the output port of Doherty amplifier. The proposed power amplifier using adaptive bias circuit and PBG has been improved the $IMD_3$ by 7.5 dBc, and the average PAR by $12\%$, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.4
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• pp.7-16
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• 1971

A negative resistance element in the form of current control can be obtained by using a pair transistor circuit. This negative resistance element can be used in the generation of square pulse, and also in the realization of pulse width modulation circuit by superposing signal current on its bias current. The each bias current of pair circuit increases alternatively according to the polarity of the input signal. In order to satisfy this condition, a modified full wave rectification circuit has been adopted for supplying the input signal. Theoritical analysis of pulse times and design guidances for practical modulation circuit parameters are presented.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.113-116
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• 2003

Confluence buffers and single flux quantum (SFQ) switches are essential components in constructing a high speed superconductive Arithmetic Logic Unit (ALU). In this work, we developed a SFQ confluence buffer and an SFQ switch. It is very important to optimize the circuit parameters of a confluence buffer and an SFQ switch to implement them into an ALU. The confluence buffer that we are currently using has a small bias margin of $\pm$11％. By optimizing it with a Josephson circuit simulator, we improved the design of confluence buffer. Our simulation study showed that we improved bias global margin of 10％ more than the existent confluence buffer. In simulations, the minimal bias margin was $\pm$33％. We also designed, fabricated, and tested an SFQ switch operating in a DC mode. The mask layout used to fabricate the SFQ switch was obtained after circuit optimization. The test results of our SFQ switch showed that it operated correctly and had a reasonably wide margin of $\pm$15％.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.77-83
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• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• 한국태양에너지학회:학술대회논문집
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• 2008.04a
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• pp.241-246
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• 2008

In this paper, we analyze the I-V curve and hot-spot phenomenon caused by solar cells' serial and parallel connected circuit. The mis-match loss of parallel interconnection with low Isc string decrease lower than serially interconnected one and temperature caused by hot-spot does. Also, mis-match loss of parallel interconnection with low Voc string increase more than serially interconnected one. The string having low Voc happened hot-spot phenomenon when open circuit. The bad solar cell in string gives revere bias to good solar cell and make hot-spot phenomenon. If we consider the mis-match loss, when designing PV module and array. the efficiency of PV system might increase.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.87-92
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• 2005

In this paper, adaptive bias circuit and PBG structure have been employed to suppress IMD and improve PAE (Power Added Efficiency) of the power amplifier. It is controlling the gate 'dc' bias voltage with the envelope of the input RF signal. and The PBG structure has been employed on the output port of power amplifier . The proposed power amplifier using adaptive bias circuit and PBG has been improved the IMG by 3 dBc, and the average PAE by $35.54\%$, respectively.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.17-20
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• 2005

We has designed, fabricated, and measured a Single flux quantum (SFQ) toggle flip-flop (TFF). The TFF is widely used in superconductive digital electronics circuits. Many digital devices, such as frequency counter, counting ADC and program counter be used TFF Specially, a program counter may be constructed based on TFF We have designed the newly TFF and obtained high bias margins on test. In this work, we used two circuit simulation tools, WRspice and Julia, as circuit optimization tools. We used XIC for a layout tool. Newly designed TFF had minimum bias margins of +/- $37\%$ and maximum bias margins of +/-$37\%$(enhanced from +/- $37\%$). The designed circuits were fabricated by using Nb technology The test results showed that the re-optimized TFF operated correctly on 100kHz and had a very wide bias margins of +/- $53\%$.