• Electronics and Telecommunications Trends
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• 제28권2호
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• pp.58-69
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• 2013

LTE 기반의 펨토셀 활용과 개발에 대한 요구는 LTE로의 이동통신 서비스가 본격화되면서, 최근 몇 년간 중요한 이슈로 자리매김하고 있다. 기지국 장비의 재설치와 주파수의 효율적인 활용 측면에서 펨토셀 기지국은 이동통신 서비스 사업자와 가입자에게 동시에 중요한 역할을 수행할 것으로 보인다. 이러한 펨토셀 기지국의 필요성을 충족시켜 주기 위해서는 펨토셀 기지국의 형상과 기능에서 그 본래의 요구를 만족시켜 주는 것이 중요하다. 무엇보다도, LTE 기반의 펨토셀 기지국은 기기의 간편한 설치와 매크로셀 기지국의 오프로딩이라는 역할을 충실히 수행할 수 있는지가 핵심적 평가 요소가 될 것이다. 이를 위해서는 펨토셀 기지국의 핵심 부품인 베이스밴드 SoC(System on a Chip) 성능 및 기능이 펨토셀 기지국 전체의 경쟁력을 판단하는 데 중요한 척도 중에 하나가 될 것이다. 본고에서는 이러한 관점에서 ETRI가 개발한 LTE 펨토셀 기지국의 베이스밴드 SoC를 중심으로 그 형상과 개발 과정을 기술하고 해외 업체들의 베이스밴드 칩셋의 형상과 개발상황에 대해서 자세히 기술하기로 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.56-64
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• 2017

In this paper, an advanced ZigBee (AZB) system for internet-of-things (IoT) applications is proposed which can support various data rates from 31.25 Kbps to 2 Mbps, and the implementation results of the AZB baseband processor are presented. Repetition coding for 32-chip direct-sequence spread spectrum (DSSS) symbol is applied for low rates under 250 Kbps to extend the coverage. Convolution coding, puncturing, and interleaving for non-DSSS symbol are performed for high rates from 500 Kbps to 2 Mbps for multi-media services. Simulation results show that the coverage increases at the rate of 51.8-77.3% for various environments compared with IEEE 802.15.4 ZigBee. AZB baseband processor was implemented in 180 nm CMOS process and total gate counts are 260K with the size of $5.8mm^2$.

• ETRI Journal
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• 제44권5호
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• pp.859-874
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• 2022

This paper presents a low-power and lightweight human body communication (HBC) receiver with an embedded dummy electrode for improved signal acquisition. The clock data recovery (CDR) circuit in the receiver operates with a low supply voltage and utilizes a clock phase inversion scheme. The receiver is equipped with a main electrode and dummy electrode that strengthen the capacitive-coupled signal at the receiver frontend. The receiver CDR circuit exploits a clock inversion scheme to allow 0.9-V operation while achieving a shorter lock time than at 3.3-V operation. In experiments, a receiver chip fabricated using 130-nm complementary metal-oxide-semiconductor technology was demonstrated to successfully receive the transmitted signal when the transmitter and receiver are placed separately on each hand of the user while consuming only 4.98 mW at a 0.9-V supply voltage.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• 제7권5호
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• pp.97-105
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• 2008

The micro capacitors are passive elements necessary to electronic circuits and wireless portable PAN(personal area network) and Mobile Communications device modules in the baseband circuits in combination with another passive and active devices. As capacitance is proportionally increased with dielectric constant and electrode areas, in addition, inversely decreased the thickness of the dielectric material, thus thin film capacitors are generally seen as a preferable means to achieve high performance and thin film capacitors are used in a variety of functional circuit devices. In this paper, propose dielectric material as AIN(Aluminium nitride) to make micro thin film capacitor, and this capacitor has the MIM(metal-insulator-metal) structure. AIN thin films are widespread applied because they had more excellent properties such as chemical stability, high thermal conductivity, electrical isolation and so on. In addition, AIN films show low frequency response for baseband signal ranges, I-V and C-V electrical characterization of a thin film micro capacitor. The above experimental test and estimated results demonstrate that the thin film capacitor has sufficient and efficient functional performance to be the baseband range frequency of general electronics circuit and passive device applications.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.669-670
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• 2006

This paper describes the functions and design technology of the T-DMB (Terrestrial Digital Multimedia Broadcasting) receiver. T-DMB is a novel broadcasting media that can provide high-quality video and audio services. In this paper, we will describe the VLSI implementation of RF, Baseband and Multimedia Chip for T-DMB Receiver. The designed DMB SoC has low power consumption and has been implemented using a standard-cell library in 0.18um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제34권8C호
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• pp.806-813
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• 2009

This paper presents a modem chip design for high-speed wireless communications. Among the high-speed communication technologies, we design the UWB (Ultra-Wideband) modem SoC (System-on-Chip) Chip based on a MB-OFDM scheme which uses wide frequency band and gives low frequency interference to other communication services. The baseband system of the modem SoC chip is designed according to the standard document published by WiMedia. The SoC chip consists of FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform), transmitter, receiver, symbol synchronizer, frequency offset estimator, Viterbi decoder, and other receiving parts. The chip is designed using 90nm CMOS (Complementary Metal-Oxide-Semiconductor) procedure. The chip size is about 5mm x 5mm and was fab-out in July 20th, 2009.

• Journal of Communications and Networks
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• 제13권1호
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• Journal of Korea Multimedia Society
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• 제18권12호
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• pp.1547-1554
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• 2015

Because there are numerous near field communication (NFC) technical standards and each standard has an independent communication protocol, an NFC software for controlling the protocols are significantly complicated. Especially, the anticollision algorithm for establishing the initial communication connection is classified into bit-oriented or time slot method according to the technical standards. Moreover, the anticollision algorithm is generally manipulated in software because of its complexity. In addition, since one host processor is shared by multiple modems in a connectivity SoC, embedding several communication modems with an NFC modem, the spare computing resources can be utilized for other modems by reducing the software cost to control the NFC modem. In this paper, we propose new design methods of the NFC modem for supporting anticollision, framing and bit rate detection in the hardware to reduce the software overhead. Therefore, the utilization of the NFC technology is enhanced in the connectivity SoC by minimizing the cost of software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제39권6호
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• pp.69-77
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• 2002

In this paper, we present the CDMA2000 1x compliant mobile station modem chip (SCom5010) implemented in a 0.18${\mu}{\textrm}{m}$ CMOS technology.[1] ARM940T cached processor. TeakLite DSP core, and other peripheral blocks are integrated with the baseband modem chip. Also we show novel verification methodologies and explain how this chip can be used as an emulation processor.

• Journal of Electrical Engineering and information Science
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• 제2권5호
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• pp.9-16
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• 1997

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.