• 센서학회지
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• 제29권4호
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• pp.275-278
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• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.302-302
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• 2011

The binary chalcogenide semiconductor Bi2Se3 is at the center of intensive research on a new state of matter known as topological insulators. It has Dirac point in their band structures with robust surface states that are protected against external perturbations by strong spin-orbit coupling with broken inversion symmetry. Such unique band configurations were confirmed by recent angle-resolved photoelectron emission spectroscopy experiments with an unwanted n-type doping effect, showing a Fermi level shift of about 0.3 eV caused by atomic defects such as Se vacancies. Since the number of defects can be reduced using the molecular beam epitaxy (MBE) method. We have prepared the Bi2Se3 film on noble metal Au(111) and semiconductor Si(111) substrates by MBE method. To characterize the film, we have introduced several surface sensitive techniques including x-ray photoemission electron spectroscopy (XPS) and micro Raman spectroscopy. Also, crystallinity of the film has been confirmed by x-ray diffraction (XRD). Using home-built scanning tunneling microscope, we observed the atomic structure of quintuple layered Bi2Se3 film on Au(111).

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.240-242
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• 2013

In this paper, novel Carbon Nanotube Gate-Elongated Tunneling Field Transistor(CNT G-E TFET) is proposed. This proposed device is designed to decrease off-current around 2~6 orders of magnitude compared to the gate-channel size matched TFET. Mechanism of CNT G-E TFET creates additional steps in energy band structure so that off-current can be reduced. Since CNT TFETs show a great probability for tunneling processes and they are beneficial for the overall device performance in terms of switching speed and power consumption, CNT G-E TFET looks pretty much promising.

• Journal of Magnetics
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• 제11권4호
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• pp.170-181
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• 2006

Spin dependent tunneling has enormously activated the field of magnetism in general, and in particular spin transport studies, in the past ten years. Thousands of articles related to the subject have appeared with many fundamental results. Importantly, there is great interest in their potential for application. There was another surge of activity in this field since the past five years - created by the theoretical prediction of a large tunnel magnetoresistance that arises due to band symmetry matched coherent tunneling in epitaxial magnetic tunnel junctions with (001) MgO barrier and experimentally well demonstrated. This further development in the field has boosted the excitement in both fundamental science as well as the possibility of application in such as magnetic random access memory, ultra sensitive read heads, biosensors and spin torque diodes. This review is a brief coverage of the field highlighting the literature that deals with magnetic tunnel junctions having epitaxial MgO tunnel barriers.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.276-283
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• 2005

Magnetic tunneling transistor (MTT) device using the amorphous n-type Si semiconductor film for base and collector consisting of the [CoFe/NiFe](free layer) and Si(top layer) multilayers was used to study the spin-dependent hot electron magnetocurrent (MC) and tunneling magnetoresistance (TMR) at room temperature. A large MC of 40.2 % was observed at the emitter-base bias voltage ( $V_{EB}$ ) of 0.62 V. The increasing emitter hot current and transfer ratio ( $I_{C}$/ $I_{E}$) as $V_{EB}$ are mainly due to a rapid increase of the number of conduction band states in the Si collector. However, above the $V_{EB}$ of 0.62 V, the rapid decrease of MC was observed in amorphous Si-based MTT because of hot electron spin-dependent elastic scattering across CoFe/Si interfaces.

• 전자공학회논문지A
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• 제30A권12호
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• 한국전기전자재료학회논문지
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• 제16권3호
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

• Journal of information and communication convergence engineering
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• 제4권2호
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• pp.84-87
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• 2006

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

• 한국정보통신학회논문지
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• 제10권6호
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• pp.1038-1044
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• 2006

초고속 통신망에서 터널링 기법은 네트워크 인증 및 데이터의 보안 지원에 있다. 이를 위해 IPSec, SOCKS V5 및 GRE 터널링 프로토콜 등을 사용하고 있다. 본 논문은 초고속 통신망에서 특정 IP 대역에 대하여 라우팅 루트를 변경시켜 유해 서비스 접속 차단 및 이용자 Needs에 따라 특정 서비스에 대한 라우팅 루트를 변경시켜 이용자가 원하는 선택적인 서비스 제공 기반을 구현하고자 하였다. 따라서 GRE프로토콜을 이용하여 GRE의 동작 원리를 측정 분석하고, 그 결과를 접속 제어 및 인증 기반 서비스에 적용하고자 한다.