• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.2C
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• pp.105-111
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• 2011

In this paper, we propose a novel Alamouti space-time transmission scheme for orthogonal frequency division multiplexing (OFDM) based asynchronous cooperative communication systems with low relay complexity. The conventional scheme requires an additional operation likes time-reversal at the relay nodes besides the simple multiplications at the relay nodes, which result in increasing the complexity of relay nodes. Unlike the conventional scheme, exploiting the simple combination of the symbols at the source node and the simple multiplications at the relay nodes, the proposed scheme achieves the second order diversity gain by obtaining the Alamouti code structure at the destination node. Simulation results show that the proposed scheme achieves the second order diversity gain and has the same bit error rate performance as the conventional scheme.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.10-19
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• 1986

This is the last part of the four-part describing the development of a packet-switched computer communication network named the KORNET. In this paper we describe the design and implementation of the packet assembler/dissassembler (PAD) protocol for the asynchronous channel service, and of the network management softwares. The line processing module-B(LPMB) system supporting the asynchronous line includes a PAD protocol, a packet mode DTE/DCE protocol converting to the X.25 protocol, and the asynchronous receiver/transmitter(ART) software. The network management software is operated in master central processing module(MCPM) which includes virtual circuit management (VCM) managing the user channel, the routing management and the high level protocol for communication between the network management center (NMC) and the network node processor(NNP). In this paper, the design, implementation and operation of the softwares for the above service functions will be described in detail.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.17-23
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• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.384-387
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• 1999

In this paper, we have proposed a testing methodology for Speed-Independent asynchronous control circuits using the self-checking property where the circuit detects certain classes of faults during normal operation. To exploit self-checking properties of Speed-Independent circuits, the Proposed methodology generates tests from the specification of the target circuit which describes the behavior of the circuit. The generated tests are applied to a fault-free and a faulty circuit, and target faults can be detected by the comparison of the outputs of the both circuits. For the purpose of efficient comparison, reachability information of the both circuits in the form of BDD's is used and operations are conducted by BDD manipulations. The identification for undetectable faults in testing is also used to increase efficiency of the proposed methodology. The proposed identification uses only topological information of the target circuit and reachability information of the good circuit which was generated in the course of preprocess. Experimental results show that high fault coverage is obtained for synthesized Speed-Independent circuits and the use of the identification process decreases the number of tests and execution time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.251-257
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• 2004

Nonvolatile FRAMs with a design rule of 0.18 ${\mu}m$ were developed for the high performance smart card. A 1Mb FRAM was embedded in place of an EEPROM and a 64Kb FRAM was embedded in place of a. SRAM. It was confirmed that the FRAMs performed the roles of the EEPROM and SRAM successfully using the asynchronous write/read operation method and the one time programming (OTP) scheme. The cycle time of the FRAM was 10 MHz, which remarkably improved the write performance of the smart card in comparison with that of the conventional smart card with an EEPROM. Additionally, a simple and smart bit-line reference scheme for the future FRAM device having a 1T1C cell type was proposed.

• The KSFM Journal of Fluid Machinery
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• v.5 no.3 s.16
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• pp.7-14
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• 2002

A new foil bearing, ViscoElastic Foil Bearing(VEFB) is suggested with the need for a high damping foil bearing. Sufficient damping capacity is a key technical hurdle to super-bending-critical operation as well as widespread use of foil bearings into turbomachinery. The super-bending-critical operation of the conventional bump foil bearing and the VEFB is examined, as well as the structural dynamic characteristics. The structural dynamic test results show that the equivalent viscous damping of the VEFB is much larger than that of the bump bearing, and that the structural dynamic stiffness of the VEFB is comparable or larger than that of the bump bearing. The results of super-bending-critical operation of the VEFB indicate that the enhanced structural damping of the viscoelastic foil dramatically reduces the vibration near the bending critical speed. With the help of increased damping resulting from the viscoelasticity, the suppression of the asynchronous orbit is possible beyond the bending critical speed.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.166-168
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• 2001

Generation by the privately owned generators, which are normally operated has occupied about 10% of total generation. Recently the small co-generation employed gas engine has been introduced and attracted public interest. For privately owned generator to be paralleled Utilities, a customer complies with Generator Parallel Operation Guideline set by Utilities and installs related protective relays. But the guideline is not specified to small co-generation, only provides parallel operation of privately owned generator. So applying this guideline, initial investment can be too high comparing to total co-generation cost. Besides there is no specified guide about ALTS, which arises asynchronous problem. In this paper we analyzed guideline and technical problem when small co-generation is paralleled. And additionally needed researching area to improve distribution of small co-generation is discussed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.3
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• pp.352-361
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• 2021

An underwater positioning method that can be applied to structures for underwater construction is being developed at the Korea Institute of Ocean Science and Technology. The method uses an extended Kalman filter (EKF) based on an inertial navigation system for precise and continuous position estimation. The observation matrix was configured to be variable in order to apply asynchronous measured sensor data in the correction step of the EKF. A Doppler velocity logger (DVL) can acquire signals only when attached to the bottom of an underwater structure, and it is difficult to install and recover. Therefore, a complex sensor device for underwater structure attachment was developed without a DVL in consideration of an underwater construction environment, installation location, system operation convenience, etc.. Its performance was verified through a water tank test. The results are the measured underwater position using an ultra-short baseline, the estimated position using only a position vector, and the estimated position using position/velocity vectors. The results were compared and evaluated using the circular error probability (CEP). As a result, the CEP of the USBL alone was 0.02 m, the CEP of the position estimation with only the position vector corrected was 3.76 m, and the CEP of the position estimation with the position and velocity vectors corrected was 0.06 m. Through this research, it was confirmed that stable underwater positioning can be carried out using asynchronous sensors without a DVL.