• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.4
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• pp.405-412
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• 2013

This paper includes new protection concepts and practices to avoid mechanical damage of three-phase transformer by asynchronous operation of synchronous generator. this failure is often caused just after synchronous generator was connected to the grid because of a malfunction of the controller or misconnections of the synchronous devices. The results of the studies on the analyzing the phenomenon of asynchronous operation experienced in Korea and rapidly detecting asynchronous state are descrived.

• Journal of IKEEE
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• v.22 no.3
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.759-762
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• 1998

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of Electrical Engineering and Technology
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• v.2 no.3
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• pp.358-365
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• 2007

This paper deals with a novel solid state controller (NSSC) for parallel operated isolated asynchronous generators (IAG) feeding 3-phase 4-wire loads in constant power applications, such as uncontrolled pico hydro turbines. AC capacitor banks are used to meet the reactive power requirement of asynchronous generators. The proposed NSSC is realized using a set of IGBTs (Insulated gate bipolar junction transistors) based current controlled 4-leg voltage source converter (CC-VSC) and a DC chopper at its DC bus, which keeps the generated voltage and frequency constant in spite of changes in consumer loads. The complete system is modeled in MATLAB along with simulink and PSB (power system block set) toolboxes. The simulated results are presented to demonstrate the capability of isolated generating system consisting of NSSC and parallel operated asynchronous generators driven by uncontrolled pico hydro turbines and feeding 3-phase 4-wire loads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.1002-1008
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• 2003

In terrestrial data broadcasting, we are just on the beginning stage in all aspects including implementation and design techniques and only asynchronous data processing has been receiving a little study. In this paper, we therefore propose an efficient processing algorithm for synchronization of asynchronous data by using trigger information to make more diverse service possible with a variety of contents. In the proposed algorithm, trigger data is encapsulated in DSM-CC section and transmitted in a form of MPEG-2 TS. The data is then separated in PC type set-top box and detached asynchronous data and trigger data are stored by the proposed algorithm. Pre-loaded asynchronous data is displayed when STC(system time clock) has the same value as PTS(presentation time stamp). Proper operation of the proposed algorithm was verified by using a content of asynchronous data with extensible markup language(XML) and a declarative application(DA) browser.

• Management Science and Financial Engineering
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• v.6 no.1
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• pp.37-63
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• 2000

An important objective of pull-based production control is to achieve synchronized and smooth production flow in a multi-stage system that is subject to uncertainty. To our knowledge, previous research has not generated a performance measure that captures this objective of pull-based probased production control system. This performance material with respect to the instant when the operation is required. We examine the issue of asynchronous waste in a two-stage kanban control system.