• Journal of Periodontal and Implant Science
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• v.31 no.3
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• pp.565-571
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• 2001

The purpose of this study is to determine if a relationship exists among osteoporosis, alveolar bone density and periodontal disease in postmenopausal osteoporotic women and postmenopausal healthy women. Twenty-two women were evaluated for this study. They were attending the postmenopausal clinic, Seoul National University Hospital and generally healthy except osteoporosis. They had experienced menopause not less than one year when we began to examine them. Bone densities of lumbar area(L2-L4) was determined by DEXA(LUNAR-expert Co,. U.S.A). We diagnosed osteoporosis when T-score was below -2.5 and healthy state when T-score was over -1. Osteoporotic(10 female), not hormone-treated group and healthy control group(12 female) were asked for their age, menopausal age, menopausal period and the number of remaining teeth and examined clinically for plaque index(PI), gingival index(GI), clinical attachment loss(CAL) on their 6 Ramfjord index teeth. Intraoral radiographs were taken in maxillary anterior zone. All films were equally exposed and developed. Each films was digitized and analysed using image processing software, Scion image. Alveolar bone regions of interest were selected and Intensity of each pixel was quantized in the array ranging from 0(white) to 255(black). The two groups were comparable with respect age, menopausal age, menopausal period and number of remaining teeth. The osteoporotic women had significantly lower alveolar bone density than controls in maxilla. But no significant difference was found with respect clinical attachment loss, plaque index and gingival index. Supported by the Ministry of Public Health and Welfare, Korea (HMP-00-CH-10-0009).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• The Journal of the Convergence on Culture Technology
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• v.6 no.4
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• pp.225-230
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• 2020

This paper highlights the influence and the importance of the syntactic-grammatical knowledge on "the reading machine", appeared in Jackendoff (1999). Due to the lack of the detailed testing and implementation in his research, this paper tests an extensive data array using a component of Google Translate, currently available freely and most widely on the internet. Although outdated, Jackendoff's paper, "Why can't Computers use English?", argues that syntactic-grammatical knowledge plays a key role in the outputs of computers and computer-based reading machines. The current research has implemented some testings of his thought-provoking examples, in order to find out whether Google Translate can handle the same problems after two decades or so. As a result, it is argued that in the field of NLP, I-language in the sense of Chomsky (1986, 1995 etc) is real and the syntactic, grammatical, and categorial knowledge is essential in the faculty of language. Therefore, it is reassured in this paper that when it comes to human language, even the most advanced "machine" is still no match for human faculty of language, the syntactic-grammatical knowledge.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• Geophysics and Geophysical Exploration
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• v.1 no.1
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• pp.57-63
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• 1998

The electrical resistivity method, one of old and widely used geophysical prospecting methods, has extended its scope to civil & environmental engineering areas. The electrical resistivity imaging technique was performed at the waste disposal site located in Junju to verify the applicability to the environmental engineering area. The dipole-dipole array, with the dipole spacing of 10 m, was applied along eight survey lines. The field data were obtained under the control of automatic acquisition softwares and topographic effects were corrected during processing stage. The processed resistivity images show that very low resistivity develops inside the disposal site and the distribution of low resistivity is exactly in accord with the boundary of the site except the river side. The depth of low resistivity zones is deeper toward the river side, which is interpreted that there is a high possibility for contaminants to be scattered to the river. From resistivity images, it was feasible to deduce the depth of waste disposal as well as the horizontal/vertical distribution of the contaminated zone, which proved the applicability of the electrical resistivity imaging technique to the environmental engineering area.

• The Journal of the Acoustical Society of Korea
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• v.41 no.4
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• pp.435-445
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• 2022

In this study, the reverberation of a bistatic sonar operated in southeastern coast in the East Sea in July 2020 was analyzed. The reverberation sensor data were collected through an LFM sound source towed by a research vessel and a horizontal line array receiver 1 km to 5 km away from it. The reverberation sensor data was analyzed by various methods including geo-plot after signal processing. Through this, it was confirmed that the angle reflected from the sound source through the scatterer to the receiver has a dominant influence on the distribution of the reverberation sound, and the probability distribution characteristics of bistatic sonar reverberation varies for each beam. In addition, parametric factors of K distribution and Rayleigh distribution were estimated from the sample through moment method estimation. Using the Kolmogorov-Smirnov test at the confidence level of 0.05, the distribution probability of the data was analyzed. As a result, it could be observed that the reverberation follows a Rayleigh probability distribution, and it could be estimated that this was the effect of a low reverberation to noise ratio.