• 대한전자공학회논문지
• /
• 제25권2호
• /
• pp.204-210
• /
• 1988

The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.

• 한국데이터정보과학회:학술대회논문집
• /
• 한국데이터정보과학회 2006년도 추계 학술발표회 논문집
• /
• pp.81-95
• /
• 2006

The usual arithmetic operations on real numbers can be extended to arithmetical operations on fuzzy intervals by means of Zadeh's extension principle based on a t-norm T. A t-norm is called consistent with respect to a class of fuzzy intervals for some arithmetic operation if this arithmetic operation is closed for this class. It is important to know which t-norms are consistent with a particular type of fuzzy intervals. Recently Dombi and Gyorbiro proved that addition is closed if the Dombi t-norm is used with two bell-shaped fuzzy intervals. A result proved by Mesiar on a strict t-norm based shape preserving additions of LR-fuzzy intervals with unbounded support is recalled. As applications, we define a broader class of bell-shaped fuzzy intervals. Then we study t-norms which are consistent with these particular types of fuzzy intervals. Dombi and Gyorbiro's results are special cases of the results described in this paper.

• 한국정보통신학회논문지
• /
• 제17권12호
• /
• pp.2921-2926
• /
• 2013

본 논문에서 제안된 십진 부동소수점 연산 장치(decimal floating-point arithmetic unit, DFP)는 L.K.Wang에 의해 제안된 십진 부동소수점 유닛을 기반으로 하여 데이터의 병렬 처리를 통해 동일한 크기의 지수를 갖는 두 오퍼랜드의 가수 영역의 고속 연산을 지원하도록 재설계 하였다. 제안된 십진 부동소수점 연산 장치는 Xilinx ISE를 이용하여 xc2vp30-7ff896 타겟 디바이스로 합성하였으며 (주)시스템센트로이드의 Flowrian을 통해 시뮬레이션 검증하였다. 제안된 방식은 L.K.Wang에 의해 제안된 설계 방식 및 참고문헌 [6]의 설계 방식과 비교하여 동일한 입력 데이터를 이용하여 시뮬레이션 검증한 결과, L.K.Wang 방식보다 약 8.4%, 참고문헌 [6]의 방식보다 약 3% 정도의 처리 속도가 향상되었다.

• 골판지포장물류
• /
• 제5권20호
• /
• pp.131-144
• /
• 1997

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
• /
• pp.268-273
• /
• 2002

In this paper, a new parallel multiplier circuit over $GF(2^m)$ has been proposed. The new multiplier is composed of polynomial multiplicative operation part and modular arithmetic operation part, irreducible polynomial operation part. And each operation has modular circuit block. For design the new proposed circuit, it develop generalized equations using frame each operation idea and show a example for $GF(2^m)$.

• Progress in Superconductivity
• /
• 제6권2호
• /
• pp.104-107
• /
• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1185-1187
• /
• 1987

Digital systems are increasingly being used in the ranges of many control engineering. The residue number system offers the possibility of high speed operation and error correction. The compact self-checking pulse-train residue arithmetic circuit is proposed. A fault tolerant digital filter is practically implemented using these proposed circuits.

• 한국산학기술학회논문지
• /
• 제19권2호
• /
• pp.185-191
• /
• 2018

본 연구는 유발된 정서가 뒤따르는 수 연산과제에 미치는 간섭현상의 종류와 크기를 확인해 보기 위해 수행되었다. 유발된 정서상태의 유지가 작업기억 요소 간 원활한 수행을 간섭할 수 있는 단계별 인지과제 처리 과정을 통해 자극유형 및 정서의 종류가 기초 연산(fundamental arithmetic operation)과제 수행에 미치는 영향을 알아 보았다. 피험자는 인구학적 변인에서 거의 차이가 없는 균질적인 대학생 집단으로 구성되었으며, 사전 연습시행에서 표정모방을 통해 유발된 정서를 유지하면서 후속되는 연산과제 수행 및 제시되는 답의 정오를 판단하도록 지침을 받았다. 분석결과, 자극유형 간에 간섭의 크기에서는 차이가 없었으나 유발된 정서의 종류 간에는 차이가 발견되었다. 유발된 정서의 시간지연 주효과가 계산과정의 어느 단계에 영향을 주었는지를 알아보기 위해, 자극 유형별로 정서 간 오류율과 지연 정반응률을 구하여 함께 분석하였는데, 긍정정서(기쁨조건)의 시간지연이 문장자극일 때에는 오류율 간 차이로, 그림자극일 때에는 지연 정반응률 간 차이로 나타남을 확인하였다. 이와 같은 결과는 유발된 긍정 정서의 영향이 부정정서(분노 및 슬픔 조건)에 비해 계산지연을 확대시키는 방향으로 나타났다는 점 외에 문장자극의 정서유발이 계산실패로 이어지기 쉬운 반면, 그림자극의 정서유발은 계산요동으로 이어지기 쉬운 특성이 있는 것으로 그 주효과의 영향이 분리될 수 있음을 시사한다고 하겠다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 ITC-CSCC -1
• /
• pp.195-198
• /
• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• 전자공학회논문지B
• /
• 제28B권7호
• /
• pp.520-534
• /
• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.