• Journal of the Korea Institute of Building Construction
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• v.10 no.1
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• pp.73-79
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• 2010

Deck plates have been widely used for steel framework due to their merits in terms of schedule reduction and work repetition. For this reason, most of the previous studies related to deck plates have focused on the development of form type and their constructability. In this study, through an actual case study and interviews with experts, a simulation model was developed using the CYCLONE method. Based on this model, this study not only analyzed the productivity of the work process of the deck plate in steel framework, but also identified the occurrence of idle time in the work process. In addition, using a sensitivity analysis, productivity and duration could be analyzed according to variation of input resources. Based on the results, this paper suggests a way to improve the productivity of deck plate work in steel frameworks. Using the model, it is expected that project managers would be able to predict the productivity and total duration of the deck plate work in the early project phase, which will enable managers to make an appropriate plan for input resources.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Resources Recycling
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• v.10 no.3
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• pp.14-22
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• 2001

For the recycle of coal fly ash generated from power stations, we developed an electrocyclone system which can separate unburned carbon form coal fly ash, based on the fact that coarse fly ash particles contain higher amount of unburned carbon and unburned carbon particles are charged positively, and pure ash particles are charged negatively on contacting each other. Additionally, guide vanes were installed in the cyclone to control the cut size. Two types of electrode, stick and grid type, were designed to investigate the effect of electrode type. Results show that by introducing an electric field inside the cyclone, the yield increases by 5 to 15e1o. But the content of unburned carbon in the clean ash does not change significantly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.781-788
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• 2017

This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.12
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• pp.519-524
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• 2019

A horizontal dust collector is used in a large wind-volume grain dryer. In this study, Computational Fluid Dynamics (CFD) was used to analyze the flow characteristics inside the dust collector, including the effects of wear on the conical hub on the dust collection performance. Recently, a horizontal cyclone dust collector was developed with a conical hub and fixed vanes at the inlet of the dust collector to generate swirl flow to separate foreign matter from the air. The dust collector is relatively small in size and easy to install, and it has a relatively low back pressure, which does not require any additional power. However, there are problems with a back pressure problem and dust deposition that are caused by the shape of the horizontal dust collector. To solve these problems, the flow characteristics were studied with internal shapes of the dust collector using three-dimensional flow analysis.

• Journal of the Korean earth science society
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• v.38 no.2
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• pp.105-114
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• 2017

Two dimensional finite element method with quadrilateral basis functions was applied to the spherical high order filter on the spherical surface limited area domain. The basis function consists of four shape functions which are defined on separate four grid boxes sharing the same gridpoint. With the basis functions, the first order derivative was expressed as an algebraic equation associated with nine point stencil. As the theory depicts, the convergence rate of the error for the spherical Laplacian operator was found to be fourth order, while it was the second order for the spherical Laplacian operator. The accuracy of the new high order filter was shown to be almost the same as those of Fourier finite element high order filter. The two-dimension finite element high order filter was incorporated in the weather research and forecasting (WRF) model as a hyper viscosity. The effect of the high order filter was compared with the built-in viscosity scheme of the WRF model. It was revealed that the high order filter performed better than the built in viscosity scheme did in providing a sharper cutoff of small scale disturbances without affecting the large scale field. Simulation of the tropical cyclone track and intensity with the high order filter showed a forecast performance comparable to the built in viscosity scheme. However, the predicted amount and spatial distribution of the rainfall for the simulation with the high order filter was closer to the observed values than the case of built in viscosity scheme.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.141-146
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• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

• Journal of the Korean Society of Mineral and Energy Resources Engineers
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• v.55 no.6
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• pp.517-526
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• 2018

In order to remove pollutants from the soil in the Ka-hak mine site, this study investigates optimization of the acid washing conditions for the soil. The soil at the site is presumed to be contaminated by diffused heavy-metal-contaminated tailings. The major heavy metal pollutants in the soil are copper, lead, and zinc. Gravels larger than 5mm in size constitute approximately 38% of the soil, and these are the least polluted by heavy metals. On the other hand, it is difficult to reduce the concentration of heavy metals in fine soils, particularly those whose sizes are less than 0.075 mm. The results of the continuous process using a hydro-cyclone show that fine soil particles consisting of at least 20% of the raw soil must be separated before the chemical soil washing process in order to achieve reliable cleaning.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.3
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• pp.326-331
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• 2010

This paper presents the design and implementation of a data acquisition system with a large number of multi-channels for manufacturing machine. The system having a throughput of 800-ch analog signals has been designed with Quartus II tool and Cyclone II FPGA. The proposed system is suitable for the large scale data handling in order to distinguish whether the operation is correct or not. The designed system is composed of a control unit, voltage divider and USB interface. To reduce the data throughput, we utilized an algorithm which can extract the same data from the achieved data. The test results of the system adapted to a manufacturing machine, show a relevant data acquisition operation of 800 channels in short time.