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http://dx.doi.org/10.6109/jkiice.2017.21.4.781

VLSI Design of Parallel Scheme for Comparison of Multiple Digital Signals  

Seo, Young-Ho (Ingenium College of Liberal Arts, Kwangwoon University)
Lee, Yong-Seok (Korea Electronics Technology Institute)
Kim, Dong-Wook (Department of Electronic Materials Engineering, Kwangwoon University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.21, no.4, 2017 , pp. 781-788 More about this Journal
Abstract
This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.
Keywords
comparator; VLSI; high-level; logic circuit; hardware design; multiple input;
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Times Cited By KSCI : 2  (Citation Analysis)
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