• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.3306-3311
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• 2011

Last Subway video surveillance system consists of a network device that is used. Through the network to transmit video data to digital conversion of analog video via a process server or a PC video to a split-screen in various forms is expressed. In recent years, multi-monitor video cameras from the same pop-up or more, such as history, structure expressed on a variety of video is required by express. The problem with these systems, video compression and transmission of many cameras, and this image data received from the server or PC to take out all the images you want to watch to occur when in order to express all of the images because of the need to decode most of the program per limit of number of channels is positioned. This limited number of channels to have a video that nothing forced, but it is likely to do so in the future performance of the hardware evolves gradually channeled images available number of channels will increase proportionately. However, as the development of hardware required for a single screen video channel will be more gradual capital. The hardware rather than relying solely on the performance of the decoded video data on the screen in order to express a more efficient utilization of shared memory for video surveillance software will provide the operating plan.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• 한국정보통신학회논문지
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• 제22권12호
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• pp.1698-1704
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• 2018

본 논문에서는 암호통신 응용을 위한 로렌츠 카오스 회로를 구현한다. 이산형 카오스 로렌츠 시스템을 구현하기 위하여, PIC18F 계열의 마이크로 콘트롤러가 사용되었으며, 제안하는 카오스 회로는, 연산증폭기 기반 아날로그 회로와는 다르게, 8 비트PIC 마이크로 콘트롤러 칩과 3개 R-2R 타입의 디지털-아날로그 변환기로 이루어진다. 마이크로 컨트롤러 포트 B, C 및 D에서 시간 파형 X, Y 및 Z가 출력되도록 하였다. 모의실험을 위하여 MATLAB 및 PROTEUS 소프트웨어 플랫폼이 사용되었다. 제안하는 회로에 대하여, MATLAB 및 프로테우스 프로그램에 의한 모의실험을 통하여 시간파형, 주파수 특성, 2차원 위상특성 해석을 실시하였다. 최종적으로, 카오스 시간파형, 2차원(2D) 어트랙터 가 얻어졌고, 카오스 신호에 기반한 아날로그 신호의 암호통신 검증을 실험을 통하여 확인 하였다.

• Biomolecules & Therapeutics
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• 제8권1호
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• pp.63-72
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• 2000

We intended to show some basic requirements for spectrum analysis of electroencephalogram (EEG) by visualizing the differences of the results according to different values of some parameters for analysis. Spectrum analysis is the most popular technique applied for the quantitative analysis of the electroen- cephalographic signals. Each step from signal acquisition through spectrum analysis to presentation of parameters was examined with providing some different values of parameters. The steps are:(1) signal acquisition; (2) spectrum analysis; (3) parameter extractions; and (4) presentation of results. In the step of signal acquisition, filtering and amplification of signal should be considered and sampling rate for analog-to-digital conversion is two-time faster than highest frequency component of signal. For the spectrum analysis, the length of signal or epoch size transformed to a function on frequency domain by courier transform is important. Win dowing method applied for the pre-processing before the analysis should be considered for reducing leakage problem. In the step of parameter extraction, data reduction has to be considered so that statistical comparison can be used in appropriate number of parameters. Generally, the log of power of all bands is derived from the spectrum. For good visualization and quantitative evaluation of time course of the parameters are presented in chronospectrogram.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.261-261
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• 2007

Wearable and ubiquitous micro systems will be greatly growing and their related devices should be self-powered in order to avoid the replacement of finite power sources, for example, by scavenging energy from the environment. With ever reducing power requirements of both analog and digital circuits, power scavenging approaches are becoming increasingly realistic. One approach is to drive an electromechanical converter from ambient motion or vibration. Vibration-driven generators based on electromagnetic, electrostatic and piezoelectric technologies have been demonstrated. Among various generator types proposed so far, piezoelectric generator possesses considerable potential in micro system. To overcome low mechanical-to- electric energy conversion, the piezoelectric device should activate in resonance mode in response to external vibration. Normally, the external vibration excretes at low frequency ranging 0.1 to 200 Hz, whereas the resonant frequencies of the devices are fixed as constant. Therefore, keeping their resonant mode in varying external vibration can be one of important points in enhancing the conversion efficiency. We investigated the possibility of use of multi-bender type piezoelectric devices. To match the external vibration frequency with the device resonant frequency, the various devices with different resonant frequency were chosen. Under an external vibration acceleration of 0.1G at 120 Hz, the device exhibited a peak-to-peak voltage of 2.8 V and a power of 0.5 mw in resonance mode.

• 대한전자공학회논문지SD
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• 제47권8호
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• pp.47-55
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• 2010

본 논문에서는 고해상도 저전력 SAR 타입 ADC(아날로그 디지털 변환기)의 면적을 획기적으로 줄이기 위해서 역 다중화기 (Demultiplexer)와 카운터 (Counter)를 이용하는 타이밍 레지스터 (Timing register) 구조를 제안하였다. 전통적으로 사용되는 쉬프트 레지스터에 기반을 둔 타이밍 레지스터 구조는 해상도가 증가될수록 면적이 급격하게 증가하고, 또한 잡음의 원인이 되는 디지털 소비 전력도 증가되는 반면, 제안하는 구조는 해상도 증가에 따른 에러 보정 회로의 면적과 소비 전력 증가를 줄일 수 있다. 0.18 um CMOS 공정을 이용하여 제작하였으며, 제안한 타이밍 레지스터 구조를 이용하여, 기존 구조 대비 5.4배의 면적 감소와 디지털 전력 최소화의 효과를 얻을 수 있었다. 설계한 12 비트 SAR ADC는 11 비트의 유효 비트 (ENOB), 2 mW (기준전압 생성 블록 포함)의 소비전력과 1 MSPS의 변환 속도를 보였으며, 레이아웃 면적은 $1mm{\times}1mm$ 이었다.

• 한국정보통신학회논문지
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• 제20권1호
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• pp.175-184
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• 2016

본 논문에서는 기존의 LCR 미터에 의한 측정방식이 아니라 C/V(capacitance to voltage) 변환 방식을 이용하여 커패시턴스를 측정하는 방법을 제안하였다. 그리고 다중채널용 초음파 프로브 진단장치를 구현하기 위해 192채널들을 6개의 MUX(multiplexer) 채널로 변환하는 아날로그 MUX 회로를 설계하였다. 각각의 MUX 채널 회로별 전압을 다시 커패시턴스로 변환하는 회로특성이 다르기 때문에 각각의 MUX 채널별 디지털전압을 커패시턴스로 변환하는 변환함수를 최소 자승법을 이용하여 유도하였다. 개발된 시제품의 성능시험결과로 1회 측정시간이 4초 이내로 측정되었고, 192개 채널들의 반복적인 측정에서 최대값, 최소값, 평균값에 대한 측정 오차값이 5% 이내의 시험결과가 제시되었다.

• 전자공학회논문지A
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• 제33A권11호
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• ETRI Journal
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• 제40권5호
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• pp.664-676
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• 2018

Given the rapidly increasing market penetration of photovoltaic (PV) systems in many fields, including construction and housing, the effective maintenance of PV systems through remote monitoring at the panel level has attracted attention to quickly detect faults that cause reductions in yearly PV energy production, and which can reduce the whole-life cost. A key point of PV monitoring at the panel level is cost-effectiveness, as the installation of the massive PV panels that comprise PV systems is showing rapid growth in the market. This paper proposes an implementation method that involves the use of a panel-level wireless PV monitoring module (WPMM), and which assesses the cost-effectiveness of this approach. To maximize the cost-effectiveness, the designed WPMM uses a voltage-divider scheme for voltage metering and a shunt-resistor scheme for current metering. In addition, the proposed method offsets the effect of element errors by extracting calibration parameters. Furthermore, a design method is presented for portable and user-friendly PV monitoring, and demonstration results using a commercial 30-kW PV system are described.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.906-909
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• 2006

본 논문은 저 전압 및 저 왜곡 스위치형 커패시터 (switched-capacitor, SC)를 적용한 새로운 형태의 몸체효과 보상형 스위치 구조를 제안한다 제안된 회로는 저 전압 SC 회로를 위해서 rail-to-rail 스위칭을 허용하며 기존의 부트스트랩된 회로 (19dB) 보다 더 우수한 총 고조파 왜곡을 가진다. 설계된 2-1 캐스케이드 시그마 델타 변조기는 통신 송수신시스템내의 오디오 코덱을 위한 고해상도 아날로그-디지털변환을 수행한다. 1단 폴드형 캐스코드 연산증폭기 및 2-1 캐스케이드 시그마 델타 변조기는 0.25 마이크론 이중 폴리 3-금속 표준 CMOS 공정으로 제작되었으며, 2.7V에서 동작한다.