• ETRI Journal
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• 제37권6호
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• pp.1176-1187
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• 2015

This work proposes a highly efficient sensorless motor driver chip for various permanent-magnet synchronous motors (PMSMs) in a wide power range. The motor driver chip is composed of two important parts. The digital part is a sensorless controller consisting mainly of an angle estimation block and a speed control block. The analog part consists of a gate driver, which is able to sense the phase current of a motor. The sensorless algorithms adapted in this paper include a sliding mode observer (SMO) method that has high robust characteristics regarding parameter variations of PMSMs. Fabricated SMO chips detect back electromotive force signals. Furthermore, motor current-sensing blocks are included with a 10-bit successive approximation analog-to-digital converter and various gain current amplifiers for proper sensorless operations. Through a fabricated SMO chip, we were able to demonstrate rated powers of 32 W, 200 W, and 1,500 W.

• International Journal of Control, Automation, and Systems
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• 제2권3호
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• pp.279-288
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• 2004

This paper presents a novel design for a tubular linear brushless permanent-magnet motor. In this design, the magnets in the moving part are oriented in an NS-NS―SN-SN fashion which leads to higher magnetic force near the like-pole region. An analytical methodology to calculate the motor force and to size the actuator was developed. The linear motor is operated in conjunction with a position sensor, three power amplifiers, and a controller to form a complete solution for controlled precision actuation. Real-time digital controllers enhanced the dynamic performance of the motor, and gain scheduling reduced the effects of a nonlinear dead band. In its current state, the motor has a rise time of 30 ms, a settling time of 60 ms, and 25% overshoot to a 5-mm step command. The motor has a maximum speed of 1.5 m/s and acceleration up to 10 g. It has a 10-cm travel range and 26-N maximum pull-out force. The compact size of the motor suggests it could be used in robotic applications requiring moderate force and precision, such as robotic-gripper positioning or actuation. The moving part of the motor can extend significantly beyond its fixed support base. This reaching ability makes it useful in applications requiring a small, direct-drive actuator, which is required to extend into a spatially constrained environment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• 한국전자파학회논문지
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• 제24권9호
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• pp.915-921
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• 2013

본 논문에서는 65 nm RF CMOS 공정을 이용한 차량 레이더용 77 GHz 저 잡음 증폭기의 설계 방법론 및 측정 결과를 제시한다. 설계한 LNA는 3단 공통소스 증폭단 구조이며, 전송선을 사용하여 입출력 임피던스 정합을 구현하였다. 3차원 전자기 시뮬레이션 시간을 단축하기 위해 전송선 EM 라이브러리를 사전에 구축하여 정합회로를 설계하였으며, 측정을 통해 제안 방법론의 정확성을 확인하였다. 제작한 저 잡음 증폭기의 최대 이득은 77 GHz에서 10 dB, 입출력 반사 손실은 -10 dB 이하이다.

• 한국지능시스템학회논문지
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• 제26권4호
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• pp.273-278
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• 2016

본 논문에서는 로렌츠 카오스 회로를 곱셈기, 커패시터, 연산증폭기, 제어저항 등을 이용하여 설계하였다. 제안하는 회로는 SPICE 프로그램을 통하여 시간파형, 주파수 특성, 위상특성 등을 해석하였고, 로렌츠 하드웨어를 구현하여서 시간파형, 주파수 특성, 위상특성, 분기도 특성을 측정하였다. 측정결과, $500k{\Omega}$ 가변 제어 저항의 조건에 따라, 로렌츠 회로는 제어저항의 특정 영역 ($10{\sim}100k{\Omega}$)에서 카오스 신호가 생성됨을 확인하였다. SPICE 모의실험 결과와 일치함을 보였고, 하드웨어의 가변저항을 변화주면서 분기도 특성을 측정하여서 저항 변화에 따라 카오스와 주기적인 분기도 형태를 나타내는 것을 확인하였다.

• 한국군사과학기술학회지
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• 제13권6호
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• pp.1071-1079
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• 2010

This paper describes the design and fabrication of a high-efficiency GaN HEMT(Gallium Nitride High-electron Mobility Transistor) Pallet power amplifier module for S-band phased array radar applications. Pallet amplifier module has a series 2-cascaded power amplifier and the final amplification-stage consists of balanced GaN HEMT transistor. In order to achieve high efficiency characteristic of pallet power amplifier module, all amplifiers are designed to the switching-mode amplifier. We performed with various PRF(Pulse Repetition Frequency) of 1, 10, 100 and 1000Hz at a fixed pulse width of $100{\mu}s$. In the experimental results, the output power, gain, and drain efficiency(${\eta}_{total}$) of the Pallet power amplifier module are 300W, 33dB, and 51% at saturated output power of 2.9GHz, respectively.

• 전기학회논문지
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• 제64권3호
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• 한국통신학회논문지
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• 제21권9호
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• pp.2470-2480
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• 1996

The energy efficiency and bandwidth efficiency are two important criterion in designing a modulation scheme Especially the constant envelope property must be considered as in the non-linear channel tht exit, for example in the nonlinear amplifiers for satellite repeater. The Q$^{2}$AM(Quadrature Quadrature Amplitude Modulation) is a new modulation scheme which combines the Q$^{2}$PSK(Quadrature Quadrature Phase Shift Keying) scheme which increases the signal space dimension and the QAM scheme which increases the bandwidth efficiency using the multi-level signal. The Q$^{2}$AM scheme has by far superior spectrum efficiency compared with the existing modulation schemes. Applying this scheme in the non-linear communication system increses the bandwidth efficiency but cannot envelop property. In this paper, a new system architecture is suggested which satisfies the large spectrum efficiency and constant envelope property by implementing the linear block coding prior to the Q$^{2}$AM modulation. the system has improved in performance by gaining the constant envelope and the additional coding gain. We able to observe the performance improvement of the suggested system(at BER=10$^{-5}$ ) of 4.4 dB for the 16-QAM and 0.7 dB for the Q$^{2}$PSK under the exact spectrum efficiency.

• 한국태양에너지학회 논문집
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• 제33권6호
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• pp.92-97
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• 2013

This paper proposes DC offset current compensation method of transformerless fuel cell/PV PCS. DC offset current is generated by the unbalanced internal resistance of the switching devices in full bridge topology. The other cause is the sensitivity of the current sensor, which is lower than DSP in resolution. If power converter system has these causes, the AC output current in the inverter will generate the DC offset. In case of transformerless grid-connected inverter system, DC offset current is fatal to grid-side, which results in saturating grid side transformer. Several simulation results show the difficulties of detecting DC offset current. Detecting DC offset current method consists of the differential amplifiers and PWM is compensated by the output of the Op amp circuit with integrator controller. PSIM simulation verifies that the proposed method is simpler and more effective than using low resolution current sensor alone.