JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Fast RSSI using Novel Logarithmic Gain Amplifiers for Wireless Communication

  • Lee, Sung-Ho (School of Electrical Engineering and INMC, Seoul National University) ;
  • Song, Yong-Hoon (School of Electrical Engineering and INMC, Seoul National University) ;
  • Nam, Sang-Wook (School of Electrical Engineering and INMC, Seoul National University)
  • Published : 2009.03.31
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Abstract

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

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References

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