• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.8
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• pp.857-864
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• 2010

In this paper, we analyse the effect of the path imbalances(gain and phase mismatches) in LINC(LInear amplification with Nonlinear Component) system, and propose a simple scheme using LUTs(Look Up Table) to compensate the path imbalances. The EVM(Error Vector Magnitude) and ACPR(Adjacent Channel Power Ratio) of the LINC system are degraded significantly by the path imbalances because it adopts an outphasing technique. The EVM and ACPR are theoretically extracted for two variables(gain and phase mismatch factors) and 2-D LUTs for those are generated based on the analysis. The efficient and simple compensation scheme for the path imbalances is proposed using the 2-D LUTs. A LINC system with the suggested compensation scheme is implemented, and the proposed method is verified with an experiment. A 16-QAM signal with 1.5 MHz bandwidth is used. Before the compensation, the path gain ratio was 95 % and phase error was $19.33^{\circ}$. The proposed scheme adjusts those values with 99 % and $0.5^{\circ}$, and improves ACPR about 18.1 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of Sensor Science and Technology
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• v.5 no.2
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• pp.29-36
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• 1996

With the three dimensional magnetic field measuring system dealt with in this paper, accurate measurements and analyses of extremely low frequency(ELF) magnetic fields caused by starting and/or operating electric devices and power installations can be conducted. To obtain high performance for lower frequency and spatial components without any distortion, the measuring system is designed as three dimensionally including the multiturn loop-type magnetic field sensors, differential amplifiers and active integrators. As the results of calibration experiments, the frequency response characteristics of the measuring system range from 8[Hz] to about 53[kHz] for each direction of x, y, z axes, and the response sensitivities are 9.54, 9.21, $10.89[mV/{\mu}T]$, respectively. The actual survey experiments by using an oscillating impulse current generator confirm a reliability of the proposed measuring system. Also, through the other experiments by using small-sized induction motors, the magnetic field intensities when starting and steady-state operating mark 15.8, $8.61[{\mu}T]$ as maximum value, respectively. And those intensities decrease steeply according as the measuring distance increases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.11
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• pp.1072-1081
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• 2012

For Ka-band satellite communication system, a new flexible payload technologies which can compensate rain attenuation have to be developed. The Ka-band satellite output power control technology enables to adjust downlink output power of satellite payload in Ka-band (19.8 ~ 22.2 GHz). In this paper, we introduce multi-beam antenna with multi-port amplifiers for Ka-band flexible output power allocation system. We have designed multi-beam antenna with array-fed reflector to form 8 beams on the Korean Peninsula. The target EIRP per beam is more than 59 dBW. The system is designed to present 6 dB boost beams for rainfall areas. Individual beams were optimized by the excited amplitude and phase of feed elements of the feed cluster. The multi-port amplifier(MPA) is one of effective approaches for flexible power allocation in combination with multi-beam antenna. In case of using MPA in multi-beam system, the inter-port isolation characteristic of MPA is important parameter to avoid interference among the output ports. In this paper, we propose a new MPA structure that consists of two $4{\times}4$ Buttler matrixes and phase/amplitude controllable power amplifier modules.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.9-17
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• 2010

Recently, there has been much interest in orthogonal frequency division multiplexing (OFDM) for next generation wireless wideband communication systems. OFDM is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. One of the main reasons to use OFDM is to increase robustness against frequency-selective fading or narrowband interference. However, in the radio systems it is also important to distortion introduced by high power amplifiers (HPA's) such as solid state power amplifier (SSPA) considered in this paper. Since the signal amplitude of the OFDM system is Rayleigh-distributed, the performance of the OFDM system is significantly degraded by the nonlinearity of the HPA in the OFDM transmitter. In this paper, we propose a canonical piecewise-linear (PWL) model based digital predistorter to prevent signal distortion and spectral re-growth due to the high peak-to-average power ratio (PAPR) of OFDM signal and the nonlinearity of HPA's. Computer simulation on an OFDM system under additive white Gaussian noise (AWGN) channels with QPSK, 16-QAM and 64-QAM modulation schemes and modulator/demodulator implemented with 1024-point FFT/IFFT, demonstrate that the proposed predistorter achieves significant performance improvement by effectively compensating for the nonlinearity introduced by the SSPA.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1059-1066
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• 2005

This paper reports an application of Doherty amplifier for efficiency improvement of feedforward power amplifier(FPA). For performance analysis, we measured 15 W average output power using WCDMA 4FA input signal with a center frequency 2.14 GHz. The applied Doherty amplifier presents the characteristics of high efficiency and low linearity in comparison to the class AB amplifier, and it was used as main amplifier of FPA fir efficiency improvement. To analyze the change of characteristic, tow Doherty amplifiers whose linearity and efficiency are different were applied. The applied FPAs are improved about $2\%$ or more performance in efficiency, but decreased in linearity on 15 W average output power. We additionally modified the coupling factor(CF) of the error loop and the error amplifier capacity for linearity improvement. Aa a result, the efficiency improvement and high linearity resulted from the change of CF and error amplifier capacity. However, we think if the linearity of Doherty amplifier were more than 35 dBc, the FPA would improve the performance about $2\%$ or more efficiency and maintain enough linearity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.65-73
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• 2003

This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.