• Journal of the Institute of Electronics Engineers of Korea TC
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• 제46권11호
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• pp.50-55
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• 2009

In this paper, a distributed amplifier is designed using distributed network synthesis that provides the optimum absorption capability of a capacitance. Transfer functions of filters, which consist of the amplifier, are synthesized by a low-pass Chebyshev approximation. Capacitances that a filter network can absorb are calculated as a function of its minimum insertion loss(MIL) and ripple. Active devices in a distributed amplifier are modeled as equivalent circuits by using their S-parameters, and their equivalent capacitances are absorbed into filter structures by properly adjusting the MIL and ripple of a transfer function. As an application example, a distributed amplifier with the gain of about 12.5dB is designed that operates over the frequency range between 0.1 and 7.5GHz. Experimental results prove that distributed network synthesis, which considers capacitance absorption capability, is useful to the design of distributed amplifiers.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.318-325
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• 2008

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제28권10호
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• Journal of electromagnetic engineering and science
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• 제17권4호
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• pp.191-196
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• 2017

Microwave wireless power transmission (MWPT) is a promising technique for low and medium power applications such as wireless charging for sensor network or for biomedical chips in case with long ranges or in dispersive media such. A key factor of the MWPT technique is its efficiency, which includes the wireless power transmission efficiency and the radio frequency (RF) to direct current (DC) voltage efficiency of RF-DC converter (which transforms RF energy to DC supply voltage). The main problem in designing an RF-DC converter is the nonlinear characteristic of Schottky diodes; this characteristic causes low efficiency, higher harmonics frequency and a change in the input impedance value when the RF input power changes. In this paper, rather than using harmonic termination techniques of class E or class F power amplifiers, which are usually used to improve the efficiency of RF-DC converters, we propose a new method called "optimal input impedance" to enhance the performance of our design. The results of simulations and measurements are presented in this paper along with a discussion of our design concerning its practical applications.

• The Journal of the Korea institute of electronic communication sciences
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• 제3권4호
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• pp.289-294
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• 2008

Affordable traffic capacity of each node in networks is expected to reach in Tb/s range in proportion to the rapid growth of Internet users. To transmit more than Tb/s per fiber pair, WDM should be used as well as existing TDM. To increase the capacity of transmission in WDM networks, there are two ways, increasing channel speed or channel quantity. To increase the channel quantity, there are two ways, narrow spacing or expanding transmission bandwidth. To expand bandwidth, ultra-broadband optical amplifier technology is necessary. In this paper, we introduce EDFA in effect at C/L band, FRA, and some optical amplifiers in effect at S band, and analyze the development trend of various amplification technologies.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제21권3호
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• pp.213-216
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• 2008

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

• Journal of Electrical Engineering and Technology
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• 제3권4호
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• pp.566-570
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• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• Journal of the Korean Institute of Intelligent Systems
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• 제26권5호
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• pp.368-374
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• 2016

This paper presents an experimental study on an electrical circuit model of the TiO2-based nano-wired memristor device for neuromophic applications. The electrical circuit equivalent model of the proposed memristor device consists of several electronics components and some passive devices including operational amplifiers, multipliers, resistors and capacitors. In order to verify the proposed design, both of simulation (using PSPICE) as well as hardware implementation were performed for the analysis of the memristor circuit with time waveforms, frequency spectra, I-V curves and power curves. The gained results from the measured data showed a good agreement with the simulation result that confirm the proposed idea.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제9권6호
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• pp.1356-1363
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• 2005

In the gyrocompass system, the use of the fiber optic gyroscope(FOG) makes this traditional system considerably attractive because it has strong points in terms of weight, power, warming-up time, and cost. In this paper, a novel digital north-finding method based upon an FOG, which can be applied to the gyrocompass system, is proposed. The analytical model for the earth signal of the FOG is described, and the earth signals passed through lock-in amplifiers are modeled. Additionally, a north-finding algorithm using two lock-in amplifier outputs is developed, and the proposed method is organized by the developed algorithm. Simulation results are included to verify the performance of the proposed method.