• 전자공학회논문지D
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• 제34D권4호
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• pp.33-39
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• 1997

The crystallization temperature of an amorphous silicon (a-Si) can be lowered down to 400.deg. C by a new method : Double-metal induced lateral crystallization (DMILC). The a-Si film was laterally crystallized from Ni and Pd deposited area, and its lateral crystallization rate reaches up to 0.2.mu.m/hour at that temperature and depends on the overlap length of Ni and Pd films; the shorter the overlap length, the faster the rate. Poly-Silicon thin film transistors (poly-Si TFT's) fabricated by DMILC at 400.deg. C show a field effect mobility of 38.5cm$^{3}$/Vs, a minimum leakage current of 1pA/.mu.m, and a slope of 1.4V/dec. The overlap length does not affect the characteristics of the poly-Si TFT's, but determines the lateral crystallization rate.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.297-300
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• 2005

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated using sputter deposited amorphous silicon (a-Si) precursor films are investigated. The a-Si films were deposited on flexible polymer substrates using argon-helium mixture gases to minimize the argon incorporation into the film. The precursor films were then laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated pMOS TFT showed field-effect mobility of $32.4cm^2/V{\cdot}s$ and on/off ratio of $10^6$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.430-431
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• 2006

This letter reports the fabrication of polycrystalline silicon thin-film transistors (poly-Si TFT) on flexible plastic substrates using amorphous silicon (a-Si) precursor films by sputter deposition. The a-Si films were deposited with mixture gas of argon and helium to minimize the argon incorporation into the film. The precursor films were then laser crystallized using XeCl excimer laser irradiation and a four-mask-processed poly-Si TFTs were fabricated with fully self-aligned top gate structure.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2052-2054
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• 2005

TFT-LCD requires to use poly silicon for High resolution and High integration. Thin film make of Poly silicon on the excimer laser-induced crystallization of PECVD(plasma-enhanced chemical vapor deposition)-grown amorphous silicon. In the thin film hydrogen affects to a device performance from bad elements like eruption, void and etc. So dehydrogenation prior to laser exposure was necessary. In this study, use RTP(Rapid Thermal Process) at various temperature from $670^{\circ}C$ to $750^{\circ}C$ and fabricate poly-silicon. it propose optimized RTP window to compare grain size to use poly silicon's SEM pictures and crystallization to analyze Raman curved lines.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.305-308
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• 2004

We present a novel process for the ultra low temperature (<150$^{\circ}C$) polycrystalline silicon (ULTPS) TFT for the flexible display applications on the plastic substrate. The sequential lateral solidification (SLS) was used for the crystallization of the amorphous silicon film deposited by rf magnetron sputtering, resulting in high mobility polycrystalline silicon (poly-Si) film. The gate dielectric was composed of thin $SiO_2$ formed by plasma oxidation and $Al_2O_3$ deposited by plasma enhanced atomic layer deposition. The breakdown field of gate dielectric on poly-Si film showed above 6.3 MV/cm. Laser activation reduced the source/drain resistance below 200 ${\Omega}$/ㅁ for n layer and 400 ${\Omega}$/ㅁ for p layer. The fabricated ULTPS TFT shows excellent performance with mobilities of 114 $cm^2$/Vs (nMOS) and 42 $cm^2$/Vs (pMOS), on/off current ratios of 4.20${\times}10^6$ (nMOS) and 5.7${\times}10^5$ (PMOS).

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.218-221
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• 2008

Bottom-gate microcrystalline silicon thin film transistors (${\mu}c$-Si:H TFTs) were fabricated on glass and transparent polyimide substrates by conventional 13.56 MHz RF plasma enhanced chemical vapor deposition at $200^{\circ}C$. The deposition rate of the ${\mu}c$-Si:H film is 24 nm/min and the amorphous incubation layer near the ${\mu}c$-Si:H/silicon nitride interface is unobvious. The threshold voltage of ${\mu}c$-Si:H TFTs can be improved by $H_2$ or $NH_3$ plasma pretreatment silicon nitride film.

• 한국산학기술학회논문지
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• 제8권4호
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• pp.738-742
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• 2007

능동형 평판디스플레이 소자를 제작하기 위해 수소화된 비정질 규소 박막트랜지스터 (a-Si:H TFT)의 상부에 화소전극을 형성하는 과정에 따른 TFT의 특성 변화를 연구하였다. 화소전극 형성 전에 1 pA 수준의 오프상태 전류 및 $10^6$ 이상의 스위칭률을 보이던 TFT에 화소전극 공정을 행하면 오프상태 전류가 10 pA 이상으로 증가하여 소자특성이 악화되었다. 이러한 소자특성의 악화는 SiNx 보호막 표면의 플라즈마 처리로 개선될 수 있었는데, 특히 $N_2$ 플라즈마가 좋은 결과를 보였다. 화소전극 공정에 의해서 누설전류가 증가하는 것은 투명전도막 증착공정 중에 SiNx 보호막 표면에 전하가 축적되어 이에 유도되는 백채널의 캐리어 축적에 기인하는 것으로 추정된다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.264-268
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• 2005

A 2.2-inch QCIF+(176${\times}$RGB${\times}$220) TFT-LCD with integrated row driver was developed using a standard amorphous silicon TFT technology. At low temperature, the integrated row driver operation is dramatically effected by the electron drift mobility reduction(■50 %) and the threshold voltage shift (■1V) of the a-Si TFT. We studied the dependency of circuit design and found that higher on-current circuit is important to guarantee good operation in wide temperature range.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.559-562
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• 2004

A 2.2-inch QCIF+ $(176{\times}RGB{\times}220)$ TFT-LCD with integrated row driver was developed using a standard amorphous silicon TFT technology. At low temperature $({\sim}-20^{\circ}C)$, the integrated row driver operation is dramatically effected by the electron drift mobility variation $({\sim}50%)$ and the threshold voltage shift $({\sim}1V)$ of the a-Si TFT. We studied the temperature dependency of the circuit design and found that higher on-current circuit is important to guarantee good operation in wide temperature range.