• Title/Summary/Keyword: a-SiH

검색결과 4,068건 처리시간 0.043초

CST 승화법을 이용한 p-type 4H-SiC(0001) 에픽텍셜층 성장과 이를 이용한 MESFET 소자의 전기적 특성 (Epitaxial Layer Growth of p-type 4H-SiC(0001) by the CST Method and Electrical Properties of MESFET Devices with Epitaxially Grown Layers)

  • 이기섭;박치권;이원재;신병철
    • 한국전기전자재료학회논문지
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    • 제20권12호
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    • pp.1056-1061
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    • 2007
  • A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

HSC-Si형성에 따른 캐패시턴스의 향상 및 인농도 특성에 관한 연구 (A Study on Capacitance Enhancement by Hemispherical Grain Silicion and Phosphorous Concentration Properties)

  • 정양희;정재영;이승희;강성준
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2000년도 추계종합학술대회
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    • pp.475-479
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    • 2000
  • The box capacitor structure with H5G-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a 0.482f${\mu}{\textrm}{m}$$^2$ for 128Mbit DRAM. An H5G-Si formation technology with seeding method, which employs Si$_2$H$_{6}$ molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled H5G-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.s.

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탄화규소 휘스커의 합성(I) : 반응기구의 율속반응 (Synthesis of Silicon Carbide Whiskers (I) : Reaction Mechanism and Rate-Controlling Reaction)

  • 최헌진;이준근
    • 한국세라믹학회지
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    • 제35권12호
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    • pp.1329-1336
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    • 1998
  • A twt -step carbothermal reduction scheme has been employed for the synthesis of SiC whiskers in an Ar or a H2 atmosphere via vapor-solid two-stage and vapor-liquid-solid growth mechanism respectively. It has been shown that the whisker growth proceed through the following reaction mechanism in an Ar at-mosphere : SiO2(S)+C(s)-SiO(v)+CO(v) SiO(v)3CO(v)=SiC(s)whisker+2CO2(v) 2C(s)+2CO2(v)=4CO(v) the third reaction appears to be the rate-controlling reaction since the overall reaction rates are dominated by the carbon which is participated in this reaction. The whisker growth proceeded through the following reaction mechaism in a H2 atmosphere : SiO2(s)+C(s)=SiO(v)+CO(v) 2C(s)+4H2(v)=2CH4(v) SiO(v)+2CH4(v)=SiC(s)whisker+CO(v)+4H2(v) The first reaction appears to be the rate-controlling reaction since the overall reaction rates are enhanced byincreasing the SiO vapor generation rate.

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열선 CVD를 이용한 a-Si:H의 c-Si표면 passivation 및 열처리 효과 분석

  • 정대영;김찬석;송준용;왕진석;박상현;이정철
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2009년도 추계학술대회 논문집
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    • pp.397-397
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    • 2009
  • c-Si wafer에 HWCVD로 증착된 a-Si:H 박막은 초기에 낮은 passivation 특성을 가지나 열처리 공정을 통해 효과적인 passivation을 가진다. 열처리 공정은 온도와 시간에 따라 큰 차이를 보인다. 이에 열선CVD를 이용하여 n type의 c-Si 기판에 a-Si:H을 증착하여 열처리 온도에 따른 Minority carrier Lifetime를 QSSPC를 통해 passivation 특성을 측정하였다. 온도는 $150^{\circ}C{\sim}270^{\circ}C$로 변화하여 측정하였다. 또한 열처리 시간을 10분씩 증가시켜 열처리 시간에 따른 passivation을 연구, 1ms에 이르는 Minority carrier lifetime을 얻었다.

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알콕사이드로부터 Sialon-SiC계 복합분말의 합성과 분말특성(I) (Synthesis ofSialon-SiC Composite Powder from Alkoxides and the Powder Properties(I))

  • 전명철;이홍림
    • 한국세라믹학회지
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    • 제27권2호
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    • pp.265-273
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    • 1990
  • Fine Si-Al-OH-C coprecipitate powders were prepared from Si(OC2H5)4, Al(i-OC3H7)3, and carbon black by a hydrolysis method before fabrication of Sialon-SiC composite powder by carbothermal reduction at 1350$^{\circ}C$ for 10h under N2/H2 mixed atmosphere. The characterization of the synthesized Sialon-SiC composite powders was performed using XRD, BET, SEM, TEM and particle size analysis methods. The average particle size and specific surface area of the synthesized Sialon-SiC composite powder were 0.13$\mu\textrm{m}$ and 20.1㎡/g, respectively when Z=1 and N2 : H2=50 : 50.

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$H_2$ 플라즈마를 이용한 SPC-Si TFT의 전기적 특성 향상 (Improvement of electrical characteristics on SPC-Si TFT employing $H_2$ plasma treatment)

  • 김용진;박상근;김선재;이정수;김창연;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.1238_1239
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    • 2009
  • 본 논문에서는 ELA poly-Si TFT보다 뛰어난 균일도를 갖고, a-Si:H TFT보다 전기적 안정도가 우수한 PMOS SPC-Si TFT의 특성을 연구하였다. SPC-Si의 계면 특성을 향상 시키기 위해 $SiO_2$ 게이트 절연막을 증착하기 전에 Solid Phase Crystalline 실리콘(SPC-Si) 채널 영역에 다양한 H2 플라즈마 처리를 해주었다. PECVD를 이용하여 100W에서 H2 플라즈마 처리를 5분 해주었을 때 SPC-Si TFT의 전기적 특성이 향상되는 것을 볼 수 있는데, $V_{TH}$가 약 -3.91V, field effect mobility가 $22.68cm^2$/Vs, 그리고 Subthreshold swing이 0.64 정도를 보였다. 또한 소자에 Hot carrier stress($V_{GS}$=14.91V, $V_{DS}$=-15V, for 2,000sec)를 주었을 때도 전기적 특성이 변하지 않았으며, 일정한 bias stress($V_{GS}$=-15V, $V_{DS}$=-10V, for 2,000sec)를 가하였을 때도 $V_{TH}$가 증가하지 않았다. 이러한 결과를 통해 SPC-Si가 poly-Si TFT보다 더욱 안정함을 알 수 있었다.

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Enhanced Delivery of siRNA Complexes by Sonoporation in Transgenic Rice Cell Suspension Cultures

  • Cheon, Su-Hwan;Lee, Kyoung-Hoon;Kwon, Jun-Young;Choi, Sung-Hun;Song, Mi-Na;Kim, Dong-II
    • Journal of Microbiology and Biotechnology
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    • 제19권8호
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    • pp.781-786
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    • 2009
  • Small interfering synthetic double-stranded RNA (siRNA) was applied to suppress the expression of the human cytotoxic-T-Iymphocyte antigen 4-immunoglobulin (hCTLA4Ig) gene transformed in transgenic rice cell cultures. The sequence of the 21-nucleotide siRNA was deliberately designed and synthesized with overhangs to inactivate the expression of hCTLA4Ig. The chemically synthesized siRNA duplex was combined with polyethyleneimine (PEl) at a mass ratio of 1:10 (0.33 ${\mu}g$ siRNA:3.3 ${\mu}g$ PEl) to produce complexes. The siRNA complexes (siRNA+PEI) were labeled with Cy3 in order to subsequently confirm the delivery by fluorescent microscopy. In addition, the cells were treated with sonoporation at 40 kHz and 419W for 90 s to improve the delivery. The siRNA complexes alone inhibited the expression of hCTLA4Ig to 45% compared with control. The siRNA complexes delivered with sonoporation downregulated the production of hCTLA4Ig to 73%. Therefore, we concluded that the delivery of siRNA complexes into plant cells could be enhanced successfully by sonoporation.

플라즈마 화학기상증착에 의해 성장된 유사 다이아몬드 나노복합체 박막의 특성 평가 (Characteristics of diamond-like nanocomposite films grown by plasma enhanced chemical vapor deposition)

  • 양원재;오근호
    • 한국결정성장학회지
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    • 제13권1호
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    • pp.36-40
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    • 2003
  • $CH_4/(C_2H_5O)_4Si/H_2$/Ar가스 혼합물을 출발 반응원료로 하여 플라즈마 화학기상증착법으로 Si 기판 위에 유사 다이아몬드 나노복합체(diamond-like nanocomposite, DLN) 박막을 증착하였다. 성장된 막의 화학구조와 미세구조를 확인하였으며 막의 마모특성을 평가하였다. 증착된 DLN 막은 다이아몬드와 유사한 a-C:H 구조와 실리카와 유사한 a-Si:O 구조가 네트워크 형태로 구성되어 있음을 확인하였으며 극도로 낮은 마모계수와 마모속도를 나타내어 내마모 코팅용 보호막으로 의 응용에 적합한 것으로 나타났다.

4H-SiC(0001) Epilayer 성장 및 쇼트키 다이오드의 전기적 특성 (4H-SiC(0001) Epilayer Growth and Electrical Property of Schottky Diode)

  • 박치권;이원재;;신병철
    • 한국전기전자재료학회논문지
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    • 제19권4호
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    • pp.344-349
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    • 2006
  • A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

양면동시증착 열선-CVD를 이용한 a-Si:H/c-Si 이종접합 태양전지 제조 (Fabrication of a-Si:H/c-Si Hetero-Junction Solar Cells by Dual Hot Wire Chemical Vapor Deposition)

  • 정대영;송준용;김경민;이희덕;송진수;이정철
    • 한국재료학회지
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    • 제21권12호
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    • pp.666-672
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    • 2011
  • The a-Si:H/c-Si hetero-junction (HJ) solar cells have a variety of advantages in efficiency and fabrication processes. It has already demonstrated about 23% in R&D scale and more than 20% in commercial production. In order to further reduce the fabrication cost of HJ solar cells, fabrication processes should be simplified more than conventional methods which accompany separate processes of front and rear sides of the cells. In this study, we propose a simultaneous deposition of intrinsic thin a-Si:H layers on both sides of a wafer by dual hot wire CVD (HWVCD). In this system, wafers are located between tantalum wires, and a-Si:H layers are simultaneously deposited on both sides of the wafer. By using this scheme, we can reduce the process steps and time and improve the efficiency of HJ solar cells by removing surface contamination of the wafers. We achieved about 16% efficiency in HJ solar cells incorporating intrinsic a-Si:H buffers by dual HWCVD and p/n layers by PECVD.