• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.475-479
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• 2000

The box capacitor structure with H5G-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a 0.482f${\mu}{\textrm}{m}$$^2$ for 128Mbit DRAM. An H5G-Si formation technology with seeding method, which employs Si$_2$H$_{6}$ molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled H5G-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.s.

• Journal of the Korean Ceramic Society
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• v.35 no.12
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• pp.1329-1336
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• 1998

A twt -step carbothermal reduction scheme has been employed for the synthesis of SiC whiskers in an Ar or a H2 atmosphere via vapor-solid two-stage and vapor-liquid-solid growth mechanism respectively. It has been shown that the whisker growth proceed through the following reaction mechanism in an Ar at-mosphere : SiO2(S)+C(s)-SiO(v)+CO(v) SiO(v)3CO(v)=SiC(s)whisker+2CO2(v) 2C(s)+2CO2(v)=4CO(v) the third reaction appears to be the rate-controlling reaction since the overall reaction rates are dominated by the carbon which is participated in this reaction. The whisker growth proceeded through the following reaction mechaism in a H2 atmosphere : SiO2(s)+C(s)=SiO(v)+CO(v) 2C(s)+4H2(v)=2CH4(v) SiO(v)+2CH4(v)=SiC(s)whisker+CO(v)+4H2(v) The first reaction appears to be the rate-controlling reaction since the overall reaction rates are enhanced byincreasing the SiO vapor generation rate.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.397-397
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• 2009

c-Si wafer에 HWCVD로 증착된 a-Si:H 박막은 초기에 낮은 passivation 특성을 가지나 열처리 공정을 통해 효과적인 passivation을 가진다. 열처리 공정은 온도와 시간에 따라 큰 차이를 보인다. 이에 열선CVD를 이용하여 n type의 c-Si 기판에 a-Si:H을 증착하여 열처리 온도에 따른 Minority carrier Lifetime를 QSSPC를 통해 passivation 특성을 측정하였다. 온도는 $150^{\circ}C{\sim}270^{\circ}C$로 변화하여 측정하였다. 또한 열처리 시간을 10분씩 증가시켜 열처리 시간에 따른 passivation을 연구, 1ms에 이르는 Minority carrier lifetime을 얻었다.

• Journal of the Korean Ceramic Society
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• v.27 no.2
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• pp.265-273
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• 1990

Fine Si-Al-OH-C coprecipitate powders were prepared from Si(OC2H5)4, Al(i-OC3H7)3, and carbon black by a hydrolysis method before fabrication of Sialon-SiC composite powder by carbothermal reduction at 1350$^{\circ}C$ for 10h under N2/H2 mixed atmosphere. The characterization of the synthesized Sialon-SiC composite powders was performed using XRD, BET, SEM, TEM and particle size analysis methods. The average particle size and specific surface area of the synthesized Sialon-SiC composite powder were 0.13$\mu\textrm{m}$ and 20.1㎡/g, respectively when Z=1 and N2 : H2=50 : 50.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1238_1239
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• 2009

본 논문에서는 ELA poly-Si TFT보다 뛰어난 균일도를 갖고, a-Si:H TFT보다 전기적 안정도가 우수한 PMOS SPC-Si TFT의 특성을 연구하였다. SPC-Si의 계면 특성을 향상 시키기 위해 $SiO_2$ 게이트 절연막을 증착하기 전에 Solid Phase Crystalline 실리콘(SPC-Si) 채널 영역에 다양한 H2 플라즈마 처리를 해주었다. PECVD를 이용하여 100W에서 H2 플라즈마 처리를 5분 해주었을 때 SPC-Si TFT의 전기적 특성이 향상되는 것을 볼 수 있는데, $V_{TH}$가 약 -3.91V, field effect mobility가 $22.68cm^2$/Vs, 그리고 Subthreshold swing이 0.64 정도를 보였다. 또한 소자에 Hot carrier stress($V_{GS}$=14.91V, $V_{DS}$=-15V, for 2,000sec)를 주었을 때도 전기적 특성이 변하지 않았으며, 일정한 bias stress($V_{GS}$=-15V, $V_{DS}$=-10V, for 2,000sec)를 가하였을 때도 $V_{TH}$가 증가하지 않았다. 이러한 결과를 통해 SPC-Si가 poly-Si TFT보다 더욱 안정함을 알 수 있었다.

• Journal of Microbiology and Biotechnology
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• v.19 no.8
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• pp.781-786
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• 2009

Small interfering synthetic double-stranded RNA (siRNA) was applied to suppress the expression of the human cytotoxic-T-Iymphocyte antigen 4-immunoglobulin (hCTLA4Ig) gene transformed in transgenic rice cell cultures. The sequence of the 21-nucleotide siRNA was deliberately designed and synthesized with overhangs to inactivate the expression of hCTLA4Ig. The chemically synthesized siRNA duplex was combined with polyethyleneimine (PEl) at a mass ratio of 1:10 (0.33 ${\mu}g$ siRNA:3.3 ${\mu}g$ PEl) to produce complexes. The siRNA complexes (siRNA+PEI) were labeled with Cy3 in order to subsequently confirm the delivery by fluorescent microscopy. In addition, the cells were treated with sonoporation at 40 kHz and 419W for 90 s to improve the delivery. The siRNA complexes alone inhibited the expression of hCTLA4Ig to 45% compared with control. The siRNA complexes delivered with sonoporation downregulated the production of hCTLA4Ig to 73%. Therefore, we concluded that the delivery of siRNA complexes into plant cells could be enhanced successfully by sonoporation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.1
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• pp.36-40
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• 2003

The diamond-like nanocomposite (DLN) thin films were deposited on Si substrates using $CH_4/(C_2H_5O)_4Si/H_2$/Ar gas mixtures as source gases by the plasma enhanced chemical vapor deposition (PECVD). The chemical structure and microstructure of grown films were investigated and their tribological properties were evaluated by a ball-on-plate type tribometer. The deposited DLN films mainly consisted of diamond-like a-C:H and quartz-like a-Si:O networks. The DLN films had a good agreement with tribological coating applications due to their extremely low friction coefficients and low wear rates.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• Korean Journal of Materials Research
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• v.21 no.12
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• pp.666-672
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• 2011

The a-Si:H/c-Si hetero-junction (HJ) solar cells have a variety of advantages in efficiency and fabrication processes. It has already demonstrated about 23% in R&D scale and more than 20% in commercial production. In order to further reduce the fabrication cost of HJ solar cells, fabrication processes should be simplified more than conventional methods which accompany separate processes of front and rear sides of the cells. In this study, we propose a simultaneous deposition of intrinsic thin a-Si:H layers on both sides of a wafer by dual hot wire CVD (HWVCD). In this system, wafers are located between tantalum wires, and a-Si:H layers are simultaneously deposited on both sides of the wafer. By using this scheme, we can reduce the process steps and time and improve the efficiency of HJ solar cells by removing surface contamination of the wafers. We achieved about 16% efficiency in HJ solar cells incorporating intrinsic a-Si:H buffers by dual HWCVD and p/n layers by PECVD.