• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.5
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• pp.746-750
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• 2015

In this paper, we propose a simulator to evaluate the performance of the semi-active laser guidance or the quadrant photodetector and to simulate the laser power reflected from a target. The laser pulse repetition frequency was generated and synchronized with the laser pulse repetition(PRF) code. To evaluate the performances of the proposed methods, we implemented a prototype system and performed experiments. As a result, the generated high voltage was variable in the range of DC 3V to 340V and has the rate of change of 2000 V/s. PRF code can be generated within 50ms ∼ 100ms and the error is implemented within 0.3ns. The laser output is synchronized with the PRF code and has a dynamic range of 23.6dB.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.60-62
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• 2019

지능형 IoT 애플리케이션들을 효과적으로 사용하기 위해서는 추론 엔진을 Edge device로 포팅하는 것이 필수적이다. 그러나 컴퓨팅 자원이 제한적인 Edge 환경에서 computational cost가 상당히 큰 CNN 추론을 실시간으로 하는 것은 쉽지 않다. 이에, CNN 추론의 하드웨어 가속화의 필요성이 제기되어 활발한 연구가 진행되고 있으며, Xilinx, Intel 등에서도 하드웨어 가속화를 도와주는 툴을 개발하여 지속적으로 업그레이드하고 있다. 본 연구에서는 CIFAR-10 데이터베이스의 테스트 이미지 10,000개를 Xilinx 사의 CNN 추론 엔진인 DPU를 사용하여 Zynq UltraScale+ 보드에서 추론해보고, DPU 아키텍처에 따른 결과를 비교·분석했다. 병렬처리 수준을 높게 한 DPU는 그렇지 않은 DPU보다 소비전력 및 자원 사용량이 3배 이상 높았지만, 1.65배 좋은 성능을 보여 Trade-off 관계를 확인할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.55-62
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• 2016

In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.4
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• pp.573-577
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• 2015

In this paper, we propose a signal processing board suitable for a semi-active laser tracking to detect an optical signal generated from the laser target designator by applying an analog trigger signal, the quadrant photodetector and a high speed ADC(analog-digital converter) sampling technique. We improved the stability by applying the averaging method to minimize the measurement error of a gaussian pulse. To evaluate the performances of the proposed methods, we implemented a prototype board and performed experiments. As a result, we implemented a frequency counter with an error 14.9ns in 50ms. PRF error code has a stability of less than 1.5% compared to the NATO standard. Applying the three point averaging method to ADC sampling, the stability of 28% in X-axis and 22% in Y-axis than one point sampling was improved.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.304-310
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• 2017

In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.

• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.320-327
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• 2023

In this study, an FPGA-based sealer inspection system was developed to inspect the sealer applied to install vehicle glass on a car body. The sealer is a liquid or paste-like material that promotes adhesion such as sealing and waterproofing for mounting and assembling vehicle parts to a car body. The system installed in the existing vehicle design parts line does not detect the sealer in the glass rotation section and takes a long time to process. This study developed a line laser camera sensor and an FPGA vision signal processing module to solve this problem. The line laser camera sensor was developed such that the resolution and speed of the camera for data acquisition could be modified according to the irradiation angle of the laser. Furthermore, it was developed considering the mountability of the entire system to prevent interference with the sealer ejection machine. In addition, a vision signal processing module was developed using the Zynq-7020 FPGA chip to improve the processing speed of the algorithm that converted the profile to the sealer shape image acquired from a 2D camera and calculated the width and height of the sealer using the converted profile. The performance of the developed sealer application inspection system was verified by establishing an experimental environment identical to that of an actual automobile production line. The experimental results confirmed the performance of the sealer application inspection at a level that satisfied the requirements of automotive field standards.