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http://dx.doi.org/10.5573/IEIESPC.2016.5.1.55

Hybrid Multi-System-on-Chip Architecture as a Rapid Development Approach for a High-Flexibility System  

Putra, Rachmad Vidya Wicaksana (Integrated Circuits Laboratory, Microelectronics Center, Institut Teknologi Bandung)
Adiono, Trio (Integrated Circuits Laboratory, Microelectronics Center, Institut Teknologi Bandung)
Publication Information
IEIE Transactions on Smart Processing and Computing / v.5, no.1, 2016 , pp. 55-62 More about this Journal
Abstract
In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.
Keywords
H-MSoC; High-flexibility system; Rapid development; Physical-SoC; Application-SoC;
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1 D. Bertozzi and L. Benini, "Xpipes: a network-onchip architecture for gigascale systems-on-chip," IEEE Circuits Syst. Mag., vol. 4, pp. 18-31, September 2004.   DOI
2 R. Abdel-Khalek and V. Bertacco, "SoCGuard: a runtime verification solution for the functional correctness of SoCs," Proc. of IEEE/IFIP VLSI System on Chip Conf., pp. 49-54, September 2010.
3 H.J. Stolberg, et al., "HiBRID-SoC: a multi-core system-on-chip architecture for multimedia signal processing applications," Proc. of Design, Automation and Test in Europe Conf. and Exhibition, pp. 8-13, March 2003.
4 H.J. Stolberg, et al., "HiBRID-SoC: a multi-core SoC architecture for multimedia signal processing," Proc. of IEEE Workshop on Signal Process. Syst., pp. 189-194, August 2003.
5 M. Berekovic, et al., "HiBRID-SoC: a multi-core architecture for image and video applications," Proc. of Int. Conf. on Image Process., pp.III 101-104, September 2003.
6 L. Friebe, et al., "HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core," Proc. of Int. SoC Conf., pp.85-88, September 2003.
7 V.C. Srinivas, et al., "A VLSI system-on-a-chip (SoC) for digital communications," Proc. of IFIP Int. Conf. on Wireless and Optical Commun. Networks, pp. 148-152, April 2006.
8 C.C. Yang, et al., "A novel methodology for multiproject system-on-a-chip," Proc. of IEEE Int. SoC Conf., pp. 308-311, September 2011.
9 R. Marculescu, et al., "Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Syst., vol. 28, pp. 3-21, January 2009.   DOI
10 S. Kumar, et al., "A network on chip architecture and design methodology," Proc. of the IEEE Comput. Soc. Annu. Symp. on VLSI, pp. 105-112, April 2002.
11 D. Kliem and S.O. Voight, "An asynchronous bus bridge for partitioned multi-SoC architectures on FPGAs," Proc. of Int. Conf. on Field Programmable Logic and Applicat., pp. 1-4, September 2013.
12 C.M. Huang, et al., "Programmable system-on-chip (SoC) for silicon prototyping," Proc. of IEEE Int. Symp. on Ind. Electron., pp. 1976-1981, July 2008.
13 C.M. Huang, et al., "Implementation and prototyping of a complex multi-project system-on-a-chip," Proc. of IEEE Int. Symp. on Circuits and Syst., pp. 2321-2324, May 2009.
14 R. Lemaire, et al., "A flexible modeling environment for a NoC-based multicore architecture," Proc. of the IEEE Int. High Level Design Validation and Test Workshop, pp. 140-147, November 2012.
15 eCos. (2015, April 8). eCos Home Page: Introduction [Online].
16 T. Adiono, et al., "Real-time WiMAX system on chip design, implementation and field test," Proc. of the IEEJ Int. Analog VLSI Workshop, pp. 1-5, November 2012.
17 Xillybus. (2015, April 8). Xillinux: A Linux distribution for Zedboard, ZyBo, MicroZed and SocKit [Online].