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http://dx.doi.org/10.6109/jkiice.2022.26.7.1071

A Security SoC embedded with ECDSA Hardware Accelerator  

Jeong, Young-Su (Department of Electronic Engineering, Kumoh National Institute of Technology)
Kim, Min-Ju (Department of Electronic Engineering, Kumoh National Institute of Technology)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.26, no.7, 2022 , pp. 1071-1077 More about this Journal
Abstract
A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.
Keywords
Security SoC; elliptic curve cryptography; ECDSA; public-key cryptography; hardware accelerator;
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  • Reference
1 J. B. Choi and K. W. Shin, "True Random Number Generator based on Cellular Automata with Random Transition Rules," Journal of Institute of Korean Electrical and Electronics Engineers, vol. 24, no.1, pp. 52-58, Mar. 2020.
2 H. J. Yang, "A Security SoC embedded with High-Performance ECC Processor," M. S. thesis, Kumoh National Institute of Technology, Gumi, Korea, 2021.
3 D. S. Kim and K. W. Shin, "An Optimized Hardware Implementation of SHA-3 Hash Functions," Journal of Institute of Korean Electrical and Electronics Engineers, vol. 22, no.4, pp. 886-895, Dec. 2018.
4 J. B. Choi, "A Scalable ECC Processor Supporting Prime Field Elliptic Curves," M. S. thesis, Kumoh National Institute of Technology, Gumi, Korea, 2020.
5 NIST, Digital Signature Standard (DSS) Federal Information Processing Standards Publication (FIPS) 186-5, Oct. 2019. [Online] Available: https://doi.org/10.6028/NIST.FIPS.186-5-draft.   DOI
6 IoT Analytics, Market Insights for the Internet of Things [Internet]. Available: https://iot-analytics.com/state-of-the-iot-2020-12-billion-iot-connections-surpassing-non-iot-for-the-first-time/.
7 M. Ahmad, The Anatomy of Security Microcon-trollers for IoT Applications, Digi-Key Electronics, Jan. 13, 2020 [Internet]. Available: https://www.digikey.com/en/articles/the-anatomy-of-security-microcontrollers-for-iot-applications.
8 Ug761 axi reference guide [Internet]. Available: http://www.xilinx.com/support/documentation/ip_documentationlug761_axi_reference_guide.pdf.
9 H. -T. Huynh, T. -K. Tran, T. -P. Dang, and T. -T. Bui, "Security Enhancement for loT Systems Based on SoC FPGA Platforms," in 4th International Conference on Recent Advances in Signal Processing Telecommunications Computing (SigTelCom), Hanoi, Vietnam, pp. 35-39, 2020.
10 S. Sugiyama, H. Awano, and M. Ikeda, "Low- Latency 256-bit Fp ECDSA Signature Generation Crypto Processor," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E101-A, no. 12, pp. 2290-2296, Dec. 2018.   DOI