• 제목/요약/키워드: Y-junction Structure

검색결과 438건 처리시간 0.025초

Trench와 FLR을 이용한 새로운 접합 마감 구조 (A New Junction Termination Structure by Employing Trench and FLR)

  • 하민우;오재근;최연익;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권6호
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    • pp.257-260
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    • 2003
  • We have proposed the junction termination structure of IGBT (Insulated Gate Bipolar Transistor) by employing trench and FLR (Field Limiting Ring), which decrease the junction termination area at the same breakdown voltage. Our proposed junction termination structure, trench FLR is verified by numerical simulator MEDICI. In 600V rated device, the junction termination area is decreased 20% compared with that of the conventional FLR structure. The breakdown voltage of trench FLR with 4 trenches is 768 V, 99 % of ideal parallel-plane junction(1-D) $BV_ceo$.

Thin Film Si-Ge/c-Si Tandem Junction Solar Cells with Optimum Upper Sub- Cell Structure

  • Park, Jinjoo
    • Current Photovoltaic Research
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    • 제8권3호
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    • pp.94-101
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    • 2020
  • This study was trying to focus on achieving high efficiency of multi junction solar cell with thin film silicon solar cells. The proposed thin film Si-Ge/c-Si tandem junction solar cell concept with a combination of low-cost thin-film silicon solar cell technology and high-efficiency c-Si cells in a monolithically stacked configuration. The tandem junction solar cells using amorphous silicon germanium (a-SiGe:H) as an absorption layer of upper sub-cell were simulated through ASA (Advanced Semiconductor Analysis) simulator for acquiring the optimum structure. Graded Ge composition - effect of Eg profiling and inserted buffer layer between absorption layer and doped layer showed the improved current density (Jsc) and conversion efficiency (η). 13.11% conversion efficiency of the tandem junction solar cell was observed, which is a result of showing the possibility of thin film Si-Ge/c-Si tandem junction solar cell.

N 버퍽층을 갖는 수퍼접합 LDMOS (Super Junction LDMOS with N-Buffer Layer)

  • 박일용
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제55권2호
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    • pp.72-75
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    • 2006
  • A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.

Electrothermal Analysis for Super-Junction TMOSFET with Temperature Sensor

  • Lho, Young Hwan;Yang, Yil-Suk
    • ETRI Journal
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    • 제37권5호
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    • pp.951-960
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    • 2015
  • For a conventional power metal-oxide-semiconductor field-effect transistor (MOSFET), there is a trade-off between specific on-state resistance and breakdown voltage. To overcome this trade-off, a super-junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature-sensing structures-diode and resistive. In this paper, a diode-type temperature-sensing structure for a TMOSFET is designed for a brushless direct current motor with on-resistance of $96m{\Omega}{\cdot}mm^2$. The temperature distribution for an ultra-low on-resistance power MOSFET has been analyzed for various bonding schemes. The multi-bonding and stripe bonding cases show a maximum temperature that is lower than that for the single-bonding case. It is shown that the metal resistance at the source area is non-negligible and should therefore be considered depending on the application for current driving capability.

Submicron device에서의 hot-carrier 열화에 관한 연구 (A study hot-carrier degradation on submicron devices)

  • 이용희;김현호;최영규;이천희
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 하계종합학술대회논문집
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    • pp.867-870
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    • 1998
  • In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

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실리콘에서 깊은 접합의 형성을 위한 알루미늄의 확산 모델 (Diffusion Model of Aluminium for the Formation of a Deep Junction in Silicon)

  • 정원채
    • 한국전기전자재료학회논문지
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    • 제33권4호
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    • pp.263-270
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    • 2020
  • In this study, the physical mechanism and diffusion effects in aluminium implanted silicon was investigated. For fabricating power semiconductor devices, an aluminum implantation can be used as an emitter and a long drift region in a power diode, transistor, and thyristor. Thermal treatment with O2 gas exhibited to a remarkably deeper profile than inert gas with N2 in the depth of junction structure. The redistribution of aluminum implanted through via thermal annealing exhibited oxidation-enhanced diffusion in comparison with inert gas atmosphere. To investigate doping distribution for implantation and diffusion experiments, spreading resistance and secondary ion mass spectrometer tools were used for the measurements. For the deep-junction structure of these experiments, aluminum implantation and diffusion exhibited a junction depth around 20 ㎛ for the fabrication of power silicon devices.

Progressive Inelastic Deformation Characteristics of Cylindrical Structure with Plate-to-Shell Junction Under Moving Temperature Front

  • Lee, Hyeong-Yeon;Kim, Jong-Bum
    • Journal of Mechanical Science and Technology
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    • 제17권3호
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    • pp.400-408
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    • 2003
  • A study on the progressive inelastic deformation behavior of the 316 L stainless steel cylindrical structure with plate-to-shell junction under moving temperature front was carried out by structural test and analysis. The structural test intends to simulate the thermal ratcheting behavior occurring at the reactor baffle of the liquid metal reactor as free surface of hot sodium pool moves up and down under plant transients. The thermal ratchet load that heats the specimen up to 550$^{\circ}C$ was applied repeatedly and residual deformation was measured. The thermal ratcheting test was carried out with two types of cylindrical structures, one with plate to-shell junction and the other without the junction to investigate the effects of the geometric discontinuities on the global ratcheting deformation. The temperature distributions of the test specimens were measured and were used for the ratcheting analysis. The ratchet deformations were analyzed with the constitutive equation of the non-linear combined hardening model. The analysis results were in good agreement with those of the structural tests.

Effect of temperature gradient on junction magnetoresistance of magnetic tunnel junction devices

  • 노성철;박민규;이여름
    • EDISON SW 활용 경진대회 논문집
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    • 제3회(2014년)
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    • pp.495-497
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    • 2014
  • Combining the quantum transport theory with new field of Spin Caloritronics, we investigate on the influence of thermal gradient on the magneto tunnel junction structure under various circumstances. The results indicate enhancement in performance of spintronic device is possible using thermal energy.

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열처리 조건에 따른 HgCdTe의 접합 특성 (HgCdTe Junction Characteristics after the Junction Annealing Process)

  • 정희찬;김관;이희철;김홍국;김재묵
    • 전자공학회논문지A
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    • 제32A권2호
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    • pp.89-95
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    • 1995
  • The structure of boron ion-implanted pn junctio in the vacancy-doped p-type HgCdTe was investigated with the differential Hall measurement. The as-implanted junction showed the electron concentration as high as 1${\times}10^{18}/cm^{3}$ and the junction depth of 0.6.mu.m. When the HgCdTe junction was heated in oven, the electron concentration near the junction decreased and the junction depth increased as the annealing temperature and time increased. The junction structure after the thermal annealing was n$^{+}$/n$^{-}$/p. For the 200.deg. C 20min annealed sample, the electron mobility was 10$^{4}cm^{2}/V{\cdot}$s near the surface(n$^{+}$), and was larger thatn 10$^{5}cm^{2}/V{\cdot}$s near the junction(n$^{+}$). The junction formation mechanism is conjectured as follows. When HgCdTe is ion-implanted, the ion energy generates crystal defecis and displaced Hg atoms HgCdTe is ion-implanted, the ion energy generates crystal defecis and displaced Hg atoms near the surface. The displaced Hg vacancies diffuse in easily by the thernal treatment and a fill the Hg vacancies in the p-HgCdTe substrate. With the Hg vacancies filled completely, the GfCdTe substrate becomes n-type because of the residual n-type impurity which was added during the wafer growing. Therefore, the n$^{+}$/n$^{-}$/p regions are formed by crystal defects, residual impurities, and Hg vacancies, respectively.

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