• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.1134-1136
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• 2012

SQLite는 임베디드 환경에 최적화된 경량형 로컬 데이터베이스 시스템으로서, 대부분의 스마트폰을 비롯한 임베디드 시스템과 사용자 애플리케이션에 라이브러리로 사용되고 있다. SQLite는 데이터베이스 시스템의 중요한 특성인 Atomic Write를 보장하기 위하여 롤백 저널(Rollback Journal)과 WAL(Write-Ahead Log)의 두 가지 저널링 알고리즘 가운데 하나를 선택하여 사용한다. 본 연구에서는 이 두 알고리즘의 동작 원리를 분석하고 동작 성능을 측정하여 그 원인을 분석하고 개선 가능성을 보인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.309-312
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• 2004

임베디드 시스템은 특별한 목적을 수행하기 위해 컴퓨터 하드웨어와 소프트웨어를 결합시킨 것이다. 임베디드 시스템은 일반 데스크탑보다 작은 규모의 하드웨어에서 운영된다. 임베디드 시스템은 파워, 공간, 메모리 등의 여러 가지 환경적 요소에 제약을 받는다. 그리고 임베디드 시스템은 실시간으로 동작하기 때문에 임베디드 시스템에서 소프트웨어의 실패는 일반 데스크탑에서보다 훨씬 심각한 문제를 발생시킨다. 따라서 임베디드 시스템은 주어진 자원을 효율적으로 사용하여야 하고 임베디드 시스템의 실패율을 낮춰야만 한다. 치명적인 문제를 발생시킬 수 있는 임베디드 시스템의 실패의 원인 중 하나가 메모리에 관련한 문제이다. 임베디드 시스템 특정상 메모리 문제는 크게 하드웨어 기반의 메모리 문제와 소프트웨어 기반의 메모리 문제로 분류된다. 소프트웨어 기반의 메모리에 관련한 문제는 Memory Leak, Freeing Free Memory, Freeing Unallocated Memory, Memory Allocation Failed, Late Detect Array Bounds Write, Late Detect Freed Memory Write 등과 같은 것들이 있다. 본 논문에서는 임베디드 시스템의 메모리 관련에 대한 문제점을 파악하고 관련 툴을 연구하여 그 문제점들을 효율적으로 해결할 수 있는 기법을 점증적으로 연구하고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.289-297
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• 2020

Although flash disks are being used widely instead of hard disks, it is difficult to optimize for effective utilization of flash disks because overwrite in place is impossible and the power consumption and time required for read, write, and erase operations are all different. One of these optimization issues is a cache management strategy to minimize write operations. The cache operates at two levels: an operating system equipped with flash disks and a translation layer within the flash disk. Most studies deal with the operating system-level cache strategy. In this study, we implement and analyse the DPW-LRU algorithm which is one of the recently proposed operating system cache replacement algorithms to apply to FTL, and grope with some improvements. As a result of the experiment, the DPW-LRU algorithm maintained superiority even in the FTL environment, and showed better performance with a slight improvement.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.77-78
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• 2009

In this paper, we study a pattern-aware write cache policy using a NAND flash memory in disk-based mobile storage systems. Our work is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. Experimental results show that our policy improves the overall I/O performance by reducing the overhead significantly from a non-volatile cache over a traditional one.

• International Journal of Computer Science & Network Security
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• v.24 no.4
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• pp.192-196
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• 2024

The memory coherence problem occurs while mapping shared virtual memory in a loosely coupled multiprocessors setup. Memory is considered coherent if a read operation provides same data written in the last write operation. The problem is addressed in the literature using different algorithms. The big question is on the correctness of such a distributed algorithm. Formal verification is the principal term for a group of techniques that routinely use an analysis that is established on mathematical transformations to conclude the rightness of hardware or software behavior in divergence to dynamic verification techniques. This paper uses UPPAAL model checker to model the dynamic distributed algorithm for shared virtual memory given by K.Li and P.Hudak. We analyse the mechanism to keep the coherence of memory in every read and write operation by using a dynamic distributed algorithm. Our results show that the dynamic distributed algorithm for shared virtual memory partially fulfils its functional requirements.

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.11a
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• pp.172-172
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• 1994

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.193-194
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• 2013