• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.336-343
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• 2002

Nowadays, after appearance of wireless network the existent internet environment is changing into the united wire/wireless network. But the present TCP regards all of the packet losses on transmission as the packet tosses due to the congestion. When it is applied on the wireless path, it deteriorates the end-to-end TCP throughput because it regards the packet loss by handoff or bit error as the packet loss by the congestion and it reduces the congestion window. In this paper, for solving these problems we propose the method that controls the performance of TCP on the wireless link by extending ECN which is used as a congestion control mechanism on the existent wire link. This is the method that distinguished the packet loss due to the congestion from due to bit error or handoff on the wireless network, so it calls the congestion control mechanism only when there occurs the congestion in the united wire/wireless network.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.1071-1074
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• 1995

This paper proposes two directional bending actator using three link, two shape memory alloys(SMA) of coil-type springs and two guide wires. By the heating of two SMA springs sequentially, the bending and stretching of the actuator is possible. Bending angle, force and repeated bending motion of actuator were measured and characterized. The performance of the actuator has been characterized for the possible application for catheter.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.383-390
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• 2008

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.111-112
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• 2013

The three-phase four-leg voltage source inverter (VSI) topology can be an interesting option for the three phase-four wire system. With an additional leg, this topology can handle the neutral current, hence the DC link capacitance can be reduced significantly. In this paper the three dimensional space vector modulation (3D SVM) in ${\alpha}{\beta}{\gamma}$ coordinates for the three-phase four-leg VSI is presented. By using the 3D SVM method, the DC link voltage can be reduced by 16% compared with the split DC link capacitor topology and the output distortion can also be reduced under the unbalanced load condition.

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2004.06a
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• pp.306-315
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• 2004

A Bridge Transported Servo Manipulator (BTSM) for Advanced spent fuel Conditioning Process (ACP) has been developed to overcome the limitation of access that is a drawback of Mechanical master-slave manipulators (MSMs) for the equipment maintenance. Wire-driven mechanisms have been adopted to increase the handling capacity to weight. The main disadvantage of the wire driven mechanism is that if one link is in motion, other links can be affected because wires and links are coupled. In this paper, the relationship between pulleys and links are formiliarized to overcome this drawbacks, Derived equations are proven and analyzed through experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.724-730
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• 2017

SpaceWire invented for spacecrafts has Time-Code defined for time synchronization over SpaceWire network. A Time-Code suffers transmission delay of 14[bit-period] and jitter up to 10[bit-period] whenever it passes through a SpaceWire link, which is the primary cause of time synchronization error. This work presents a simple method to improve the time synchronization which uses two extended Time-Codes. Nodes on a SpaceWire network can find how much delay and jitter a received Time-Code has suffered while it passes through the network, and they can correct time synchronization error with this information. The proposed method was validated in a simulation environment developed based on OMNeT++. The simulation result showed that time synchronization error less than a few bit-periods can be achieved. The proposed method is cost effective and suitable for small-scale SpaceWire network systems.

• Korean Journal of Computational Design and Engineering
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• v.15 no.5
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• pp.383-392
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• 2010

The purpose of this study is to develop three Judo-doll systems for enhancement of Judo's performance. Traditional Judo training requires a human training partner. Unfortunately it is not always easy to find one. Multifunctional Judo-doll training system has therefore been developed, and is described here. The system consists of a dummy, a power generating mechanism, and kinematic links. The power-generating mechanism generates forces similar to those of a human, by adjusting deadweights and controlling powderbrake's forces. The powderbrake force is controlled by the microprocessor according to the exercise scenario. The kinetic links, which mimic a human training partner's motions, has been developed based on a $Vicon^{TM}$ system's analysis of the movement of human training partners. This mechanism whose name is "L link-wire" consists of L type links, wire, roller, and dead weight. This mechanism generates the force that leads the link to the neutral position regardless the link is pushed or pulled. The lifting mechanism that lifts the doll when the one-armed shoulder throw skill is applied is also developed. A 32-bit microprocessor controls the whole system; it reads the loadcell data, controls the electromagnetic force, and communicates with a PC via Bluetooth. The training history, including loadcell data, date, and training time, is stored in the PC for analysis. This training system can be used to enhance the Judo performance of any self training player.