• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1223-1224
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.609-610
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.755-756
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• 2011

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.909-910
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• 2011

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.75-81
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• 2015

In this paper, numerical analysis by finite element method and parameter design by the Taguchi method were used to reduce warpage of a two passive components embedded double side substrate for PoP(Package on Package). The effect of thickness of circuit layers (L1, L2) and thickness of solder resist (SR_top, SR_BTM) were analyzed with 4 variations and 3 levels(minimum, average and maximum thickness) to find optimized thickness conditions. Also, paste effect of solder resist on unit area of top surface was analyzed. Finally, experiments was carried out to prove numerical analysis and the Taguchi method. Based on the numerical and experimental results, it was known that circuit layer in ball side of substrate was the most severe determining deviation for reducing warpage. Buried circuit layer in chip side, solder resist and were insignificant effects on warpage relatively. However, warpage decreased as circuit layer in ball side thickness increased but effect of solder resist and circuit layer in chip side thickness were conversely.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.29-33
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• 2019

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

• Transactions of Materials Processing
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• v.32 no.6
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• pp.367-375
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• 2023

Composite materials, known for their excellent mechanical properties and lightweight characteristics, are applied in various engineering fields. Recently, efforts have been made to develop an automotive battery protection panel using a plain-woven composite composed of glass fiber and polypropylene to reduce the weight of automobiles. However, excessive warpage occurs during the GF/PP compression molding process, which makes car assembly challenging. This study aims to develop a model that predicts the warpage during the compression molding process. Obtaining out-of-plane properties such as elastic or shear modulus, essential for predicting warpages, is tricky. Existing mechanical methods also have limitations in calculating these properties for woven composite materials. To address this issue, finite element analysis is conducted using representative volume elements (RVE) for woven composite materials. A warpage prediction model is developed based on the estimated physical properties of GF/PP composite materials obtained through representative volume elements. This model is expected to be used for reducing warpages in the compression molding process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.35-42
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• 2015

Injection molding is a high efficient manufacturing technology for producing plastic parts. On the other hand, the warpage of molded plastic parts is an ubiquitous problem in the injection molding process. The main objective of this study was to minimize the amount of warpage occurring in the injection molding process of a hopper of ATDPS made of crystalline polymer (PP) instead of amorphous polymer (ABS). The moldflow CAE simulation was conducted for the molding process of the hopper to clarify the injection moldability, shear rate, shear stress, warpage by changing the gate shape and the number of ribs installed on the top of the hopper flange. The wide gate shape of runner system and multiple rib installation were found to be useful for minimizing the warpage of the hopper. The validity of the CAE simulations was supported by the injection molding experiment for the optimized design case.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.8
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• pp.3625-3630
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• 2013

The modularization accomplished a big contribution in cost down and assembly-time shortening and the quality increase. But few improvements were made to this design largely due to the inflexibility of steel. In recent years, door modules made of PP-LFT material is manufactured using injection molding method. As a result, the plastic door modules allow more flexibility of door shape and become lighter. Warpage is generally large in the molded plastic door carrier plate due to the limitation of gate location and the fiber orientation. So after a few test injection the mold compensation processing for the improvement of an assembly characteristic. This research was performed to determine the factors that contribute to warpage for a injection-molded door carrier plate and presented differences in three mesh types of meshing method and its results. as a result we can improve process of tooling modification can reduce process of trial and error.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.