• Journal of the Korean Society of Visualization
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• v.13 no.3
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• pp.24-28
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• 2015

The temperature of the wafer batch in the furnace was calculated and its visualized temperature field was analyzed. The main heat transfer mechanisms from the heater wall to the wafers were radiation and conduction, and the finite difference method was used to analyze the complex heat transfer including those two mechanisms. The visualized temperature field shows that the direction of the heat flux in the wafer batch varies during the heating process, and the heat in the wafer batch diffuses faster by conduction within the wafer than by radiation between the wafers, in the condition of the constant temperature at the heater wall and cap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.211-213
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• 1999

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.94-98
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• 2012

The behavior of ozone micro bubble cleaning system was investigated to evaluate the solution as a new method of solar cell wafer cleaning in comparison with former conventional RCA cleaning. We have developed the ozone dissolution system in the ozonated water for more efficient cleaning conditions. The optimized cleaning conditions for solar cell wafer process were 10 ppm of ozone concentration and 12 minutes in cleaning periods, respectively. We have confirmed the cleaning reliability and cell efficiencies after ozone micro bubble cleaning. Using this new cleaning technology, it was possible to obtain higher efficiency, higher productivity, and fast tact time for applying cleaning in the fields on bare ingot wafer, LED wafers as well as the solar cell wafer.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.1
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• pp.175-183
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• 1994

To investigate thermophoretic effect on particle deposition, average deposition velocity toward a horizontal wafer surface in vertical airflow is measured keeping the wafer surface temperature different from the surrounding air temperature. In the present measurement, the temperature difference is maintained in the range from -10 to $4^{\circ}$ C Polystyrene latex (PSL) spheres of diameter between 0.3 and 0.8 .mu.m are used for the experiment. The number of particles deposited on a wafer surface is estimated from the measurements using a wafer surface scanner (PMS SAS-3600). Experimental data are compared with prediction model results.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.555-556
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• 2006

In recent years, the higher flatness level in wafer shape has been strictly demanded with a high integration of the semiconductor devices. It has become difficult for a conventional wafer preparing process to satisfy those demands. In order to meet those demands, surface grinding with in-feed grinder is adopted. In an in-feed grinding method, a chuck table fur fixing a semiconductor wafrr rotates on its rotation axis with a slight tilt angle to the rotation axis of a cup shaped grinding wheel and the grinding wheel in rotation moves down to grind the wafer. So, stability of the grinder structure is very important to aquire a wafer of good quality. This paper describes the features of the in-feed grinder and some FEM analysis results of the grinder structure.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.6
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• pp.146-151
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• 2011

Wax spin coating is a part of several wafer handling processes in the silicon wafer polishing station. It is important to ensure the wax layer free of contamination to achieve the high degree of planarization on wafers after wafer polishing. Three-dimensional air flow characteristics in a wax spin coater are numerically investigated using computational fluid dynamics techniques. When the bottom of the wax spin coater is closed, there exists a significant recirculation zone over the rotating ceramic block. This recirculation zone can be the source of wax layer contamination at any rotational speed and should be avoided to maintain high wafer polishing quality. Thus, four air suction ducts are installed at the bottom of the wax spin coater in order to control the air flow pattern over the ceramic block. Present computational results show that the air suction from the bottom is quite an effective method to remove or minimize the recirculation zone over the ceramic block and the wax coating layer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.11-16
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• 2008

In this paper, firstly we made of the rapid thermal processor equipment with the specifically useful structure to measure wafer stress. Secondly we made of the laser interferometry to inspect the wafer surface curvature based on the large deformation theory. And then the wafer surface fringe image was obtained by experiment, and the full field stress distribution of wafer surface comes into view by signal processing with thining and pitch mapping. After wafer was ground by 1mm and polished from the back side to get easily deformation, and it was heated by three to four times thermal treatments at about 1000 degree temperature. Finally the severe deformation between wafer before and after the heat treatment was shown.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.410-413
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• 2009

Wafer pre-alignment is to find the center and the orientation of a wafer and to move the wafer to the desired position and orientation. In this paper, an area camera based pre-aligning method is presented that captures 8 wafer images regularly during 360 degrees rotation. From the images, wafer edge positions are extracted and used to estimate the wafer's center and orientation using least square circle fitting. These information are utilized for the proper alignment of the wafer.