• Tribology and Lubricants
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• 제35권3호
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• pp.176-182
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• 2019

The primary objective of this study is to treat a monocrystalline silicon (Si) wafer having a thickness of $279{\mu}m$ by employing the ultrasonic nanocrystal surface modification (UNSM) technology for improving the efficiency and service life of nano-electromechanical systems (NEMSs) and micro-electromechanical systems (MEMSs) by enhancing of wear and corrosion resistances. The wear and corrosion resistances of the Si wafer were systematically investigated before and after UNSM treatment, wherein abrasive, oxidative and spalling wear mechanisms were applied to the as-received and subsequently UNSM-treated Si wafer. Compared to the asreceived state, the wear and corrosion resistances of the UNSM-treated Si wafer are found to be enhanced by about 23% and 14%, respectively. The enhancement in wear and corrosion resistances after UNSM treatment may be attributed to grain size refinement (confirmed by Raman spectroscopy) and modified surface integrity. Furthermore, it is observed that the Raman intensity reduced significantly after UNSM treatment, whereas neither the Raman shift nor new phases were found on the surface of the UNSM-treated Si wafer. In addition, the friction coefficient values of the as-received and UNSM-treated Si wafers are found to be about 0.54 and 0.39, respectively. Hence, UNSM technology can be effectively incorporated as an alternative mechanical surface treatment for NEMSs and MEMSs comprising Si wafers.

• 한국정보과학회논문지:소프트웨어및응용
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• 제31권6호
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• pp.792-798
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• 2004

본 논문에서는 웨이퍼 영상에서 다이 위치를 인식하기 위한 새로운 코너점 검출 방법을 제안한다. 웨이퍼 다이 위치 인식은 WSCSP(Wafer Scale Chip Scale Packaging)기술에 필수적인 과정으로서 웨이퍼 윗면의 다이 패턴을 얼마나 정확히 인식하느냐에 따라서 후 공정의 정확도가 결정된다. 본 논문에서는 정확한 다이 위치를 인식하기 위하여 계층적 명암 영상 코너 검출 방법을 제안한다. 새로운 코너 검출자는 코너 영역을 마스크 크기에 따라서 동심원으로 나누어 각각의 동심원에서의 코너성과 방향성을 구하여 정확한 코너점을 검출하도록 하였다. 또한 계층적 구조를 가지고 처리하여 기존의 명암 영상코너 검출자 보다 더 빠른 처리 속도를 얻을 수 있도록 하였다.

• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• 소성∙가공
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• 제13권3호
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• pp.225-229
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• 2004

Chemical Mechanical Polishing(CMP) process becomes one of the most important semiconductor processes. But the basic mechanism of CMP still does not established. Slurry fluid dynamics that there is a slurry film between a wafer and a pad and contact mechanics that a wafer and a pad contact directly are the two main studies for CMP. This paper based on the latter one, especially on the abrasion wear model. Material Removal Rate(MRR) is calculated using the trajectory length of every point on a wafer during the process time. Both the rotational velocity of a wafer and a pad and the wafer oscillation velocity which has omitted in other studies are considered. For the purpose of the verification of our simulation, we used the experimental results of S.H.Li et al. The simulation results show that the tendency of the calculated MRR using the relative velocity is very similar to the experimental results and that the oscillation effect on MRR at a real CMP condition is lower than 1.5%, which is higher than the relative velocity effect of wafer, and that the velocity factor. not the velocity itself, should be taken into consideration in the CMP wear model.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.672-675
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• 2005

To imprint 70-nm wide line-patterns, we used a newly developed ultraviolet nanoimprint lithography (UV-NIL) process in which an elementwise patterned stamp (EPS), a large-area stamp, and pressurized air are used to imprint a wafer in a single step. For a single-step UV-NIL of a 4' wafer, we fabricated two identical $5'\times5'\times0.09'(W{\times}L{\times}H)$ quartz EPSs, except that one is with nanopatterns and the other without nanopatterns. Both of them consist of 16 small-area stamps, called elements, each of which is $10\;mm\;\times\;10\;mm$. UV-curable low-viscosity resin droplets were dispensed directly on each element of the EPSs. The volume and viscosity of each droplet are 3.7 nl and 7 cps. Droplets were dispensed in such a way that no air entrapment between elements and wafer occurs. When the droplets were fully pressed between ESP and wafer, some incompletely filled elements were observed because of the topology mismatch between EPS and wafer. To complete those incomplete fillings, pressurized air of 2 bar was applied to the bottom of the wafer for 2 min. Experimental results have shown that nanopatterns of the EPS were successfully transferred to the resin layer on the wafer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• Tribology and Lubricants
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• 제32권2호
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• pp.67-71
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• 2016

This study investigates the characteristics of the sapphire wafer chemical mechanical polishing (CMP) process. The material removal rate is one of the most important factors since it has a significant impact on the production efficiency of a sapphire wafer. Some of the factors affecting the material removal rate include the pressure, platen speed and slurry. Among the factors affecting the CMP process, we analyzed the trends in the material removal rate and surface roughness, which are mechanical factors corresponding to both the pressure and platen speed, were analyzed. We also analyzed the increase in the material removal rate, which is proportional to the pressure and platen speed, using the Preston equation. In the experiment, after polishing a 4-inch sapphire wafer with increasing pressure and platen speed, we confirmed the material removal rate via thickness measurements. Further, surface roughness measurements of the sapphire wafer were performed using atomic force microscopy (AFM) equipment. Using the measurement results, we analyzed the trends in the surface roughness with the increase in material removal rate. In addition, the experimental results, confirmed that the material removal rate increases in proportion to the pressure and platen speed. However, the results showed no association between the material removal rate and surface roughness. The surface roughness after the CMP process showed a largely consistent trend. This study demonstrates the possibility to improve the production efficiency of sapphire wafer while maintaining stable quality via mechanical factors associated with the CMP process.

• 한국결정성장학회지
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• 제11권3호
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• pp.89-95
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• 2001

규소 결정의 용융 온도 근처인 $1350^{\circ}C$에서 Ar과 $O_{2}$gas를 이용하여 규소 wafer의 열처리시 vacancy ty[e 결함의 거동에 대해 알아보았다. 이 열처리에서는 wafer의 표면보다 wafer내부에서 결함의 용해속도가 매우 높음을 확인하였다. 이는 $1350^{\circ}C$에서는 규소내의 평형산소농도가 대부분의 CZ silicon에서의 산소농도보다 높아 산소의 understaturation현상과 silicon interstitial농도의 영향에 기인된 것으로 예상된다. 열처리 분위기의 영향을 알아보기 위하여 Ar과 $O_{2}$ 분위기에서 열처리한 결과 vacancy type 결함의 용해속도는 wafer의 내부에서는 차이가 없었고, wafer의 표면에서는 Ar이 $O_{2}$의 경우보다 결함의 용해속도가 높았다. $O_{2}$의 경우에는 표면산화막 성장시 유입된 silicon interstitial의 농도가 높아 결함의 용해속도가 떨어지는 것으로 판단된다. 이는 기존 연구에서 예상된 silicon interstitial이 vacancy cluster로 알려진 결정결함의 제거에 기여한다는 예상과는 상반된다. 본 연구의 결과 silicon interstitial의 존재는 void외부 산화막의 용해속도를 늦추어 결함 용해속도를 떨어뜨리는 것으로 예상된다.

• 한국진공학회지
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• 제14권2호
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• pp.91-96
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• 2005

양성자 주입과 웨이퍼접합기술을 접목한 ion-cut기술로서 SOI 웨이퍼를 제조하는 기술을 개발하였다. SRIM 전산모사에 의하면 일반 SOI 웨이퍼 (200nm SOI, 400nm BOX) 제조에는 65keV의 양성자주입이 요구된다. 웨이퍼분리를 위한 최적 공정조건을 얻기 위해 조사선량과 열처리조건(온도 및 시간)에 따른 blistering 및 flaking 등의 표면변화를 조사하였다. 실험결과 유효선량범위는 $6\~9times10^{16}H^+/cm^2$이며, 최적 아닐링조건은 $550^{\circ}C$에서 30분 정도로 나타났다. RCA 세정법으로서 친수성표면을 형성하여 웨이퍼 직접접합을 수행하였으며, IR 조사에 의해 무결함접합을 확인하였다 웨이퍼 분리는 예비실험에서 정해진 최적조건에서 이루어졌으며, SOI층의 안정화를 위해 고온열처리($1,100^{\circ}C,\;60$분)를 시행하였다. TEM 측정상 SOI 구조결함은 발견되지 않았으며, BOX(buried oxide)층 상부계면상의 포획전하밀도는 열산화막 계면의 낮은 밀도를 유지함을 확인하였다.

• 산업경영시스템학회지
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• 제46권2호
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.