• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.195-201
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• 2000

Current Status: Good Electrical performance for high speed device, Solder joint reliability-Passed 1600 cycles for 4M SRAM(3.27mm DNP),-Passed 400 cycles for large die(5.71 mm DNP), Future Plan: Improving Board Level Reliability for large die size, Lead free solder evaluation.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.77-84
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• 2006

Surface roughness and wafer-level thickness distribution of the non-cyanide Au bumps were characterized with variations of the electroplating current density and the bath temperature. The Au bumps, electroplated at $3mA/cm^{2}\;and\;5mA/cm^{2}$, exhibited the surface roughness of $80{\sim}100nm$ without depending on the bath temperature of $40^{\circ}C\;and\;60^{\circ}C$. The Au bumps, electroplated with $8mA/cm^{2}$ at $40^{\circ}C\;and60^{\circ}C$, exhibited the surface roughness of 800nm and $80{\sim}100nm$, respectively. Wafer-level thickness deviation of the Au bumps became larger with increasing the current density from $3mA/cm^{2}\;to\;8mA/cm^{2}$. More uniform thickness distribution of the Au bumps was obtained at a bath temperature of $60^{\circ}C$ than that of $40^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.1-7
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• 2018

As the performance and density of IC (integrated circuit) devices increase, power and signal integrities in the global interconnects of advanced packaging technologies are becoming more difficult. Thus, the global interconnect technologies should be designed to accommodate increased input/output (I/O) counts, improved power grid network integrity, reduced RC delay, and improved electrical crosstalk stability. This requirement resulted in the fine-pitch interconnects with a low-k dielectric in 3D packaging or wafer level packaging structure. This paper reviews an organic-inorganic hybrid material as a potential dielectric candidate for the global interconnects. An organic-inorganic hybrid material called polysiloxane can provide spin process without high temperature curing, an excellent dielectric constant, and good mechanical properties.

• Journal of the Korean institute of surface engineering
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• v.36 no.2
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.57-67
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• 2022

The curing characteristics of naphthalene type epoxy resin systems according to the change of curing agent were investigated to develop a new next-generation EMC(Epoxy Molding Compound) with excellent warpage characteristics, low thermal expansion, and excellent fluidity for WLP(Wafer Level Package). As epoxy resins, DGEBA, which are representative bisphenol type epoxy resins, NE-16, which are the base resins of naphthalene type epoxy resins, and NET-OH, NET-MA, and NET-Epoxy resins newly synthesized based on NE-16 were used. As a curing agent, DDM (Diamino Diphenyl Methane) and CBN resin with naphthalene moiety were used. The curing reaction characteristics of these epoxy resin systems with curing agents were analyzed through thermal analysis experiments. In terms of curing reaction mechanism, DGEBA and NET-OH resin systems follow the nth curing reaction mechanism, and NE-16, NET-MA and NET-Epoxy resin systems follow the autocatalytic curing reaction mechanism in the case of epoxy resin systems using DDM as curing agent. On the other hand, it was found that all of them showed the nth curing reaction mechanism in the case of epoxy resin systems using CBN as the curing agent. Comparing the curing reaction rate, the epoxy resin systems using CBN as the curing agent showed a faster curing reaction rate than them with DDM as a hardener in the case of DGEBA and NET-OH epoxy resin systems following the same nth curing reaction mechanism, and the epoxy resin systems with a different curing mechanism using CBN as a curing agent showed a faster curing reaction rate than DDM hardener systems except for the NE-16 epoxy resin system. These reasons were comparatively explained using the reaction rate parameters obtained through thermal analysis experiments. Based on these results, low thermal expansion, warpage reduction, and curing reaction rate in the epoxy resin systems can be improved by using CBN curing agent with a naphthalene moiety.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.41-48
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• 2018

The quantitative interfacial adhesion energy measurement method of copper redistribution layer and WPR dielectric interface were investigated using $90^{\circ}$ peel test, 4-point bending test, double cantilever beam (DCB) measurement for FOWLP Applications. Measured interfacial adhesion energy values of all three methods were higher than $5J/m^2$, which is considered as a minimum criterion for reliable Cu/low-k integration with CMP processes without delamination. Measured energy values increase with increasing phase angle, that is, in order of DCB, 4-point bending test, and $90^{\circ}$ peel test due to increasing roughness-related shielding and plastic energy dissipation effects, which match well interfacial fracture mechanics theory. Considering adhesion specimen preparation process, phase angle, measurement accuracy and bonding energy levels, both DCB and 4-point bending test methods are recommended for quantitative adhesion energy measurement of RDL interface depending on the real application situations.