• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.1
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• pp.61-65
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• 2010

A commercially available soft PZT wafer that is poled in thickness direction is subjected to longitudinal tensile stress loading in both short and open-circuit conditions. Variations of electric displacement in thickness direction and in-plane strains are measured over time during the loading. Different material responses in the two electrical boundary conditions are explained by the effects of piezoelectrically produced internal electric field on linear material moduli and domain switching mechanisms. Finally, a free energy model of normal distribution is introduced to explain the observed creep behavior, and its predictions are compared with experimental observations.

• Journal of Sensor Science and Technology
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• v.13 no.6
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• pp.430-435
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• 2004

The resolution of the accelerometer, fabricated with MEMS technology is mainly affected by mechanical and electrical noise. To reduce mechanical noise, we have to increase mass of the structure part and quality factor related with the degree of vacuum packaging. On the other hand, to increase mass of the structure part, the thickness of the structure must be increased and ICP-RIE is used to fabricate the high aspect ratio structure. At this time, footing effect make the sensitivity of the accelerometer decreasing. This paper presents a hybrid SOG(Silicon On Glass) Process to fabricate a lateral silicon accelerometer with differential capacitance sensing scheme which has been designed and simulated. Using hybrid SOG Process, we could make it a real to increase the structural thickness and to prevent the footing effect by deposition of metal layer at the bottom of the structure. Moreover, we bonded glass wafer to structure wafer anodically, so we could realize the vacuum packaging at wafer level. Through this way, we could have an idea of controlling of quality factor.

• Design & Manufacturing
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• v.18 no.2
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• pp.9-16
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• 2024

Recently, there has been extensive research conducted on the miniaturization of semiconductors and the improvement of their integration to achieve high-quality and high-performance electronic devices. To integrate and miniaturize multiple semiconductors, thin and precise wafers are essential. The backgrinding process, which involves high-precision processing, is necessary to achieve this. The backgrinding system is used to grind and polish the back side of the wafer to reduce its thickness to ㎛ units. This enables the high integration and miniaturization of semiconductors and a flattening process to allow for detailed circuit design, ultimately leading to the production of IC chips. As the backgrinding system performs precision processing at the ㎛ unit, it is crucial to determine the stability of the equipment's rigidity. Additionally, the flatness and surface roughness of the processed wafer must be checked to confirm the processability of the backgrinding system. IIn this paper, the goal is to verify the processability of the back grinding system by analyzing the natural frequency and resonance frequency of the equipment through computer simulation and measuring and analyzing the flatness and surface roughness of wafers processed with backgrinding system. It was confirmed whether processing damage occurred due to vibration during the backgrinding process.

• Journal of Korea Foundry Society
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• v.33 no.2
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.9
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• pp.438-443
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• 2001

In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.192-194
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• 1993

In this paper, a silicon piezoresistive accelerometer of which the cantilevers have uniform thickness is designed and fabricated with SOI wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW etchant. The fabrication processes are that of the frontside processes including the etching of the cantilevers and the doubleside alignment holes, the diffusion of the piezoresisters and patterning of the contact windows, and the metal connection process, and that of the backside processes including the etching of the shallow cavity and the seismic mass. Because of the uniformity of thickness, the performance of the accelerometer fabricated with SOI wafer is expected to be better than that of accelerometer fabricated by the time-controlled etching method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.76-84
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• 1994

The characteristics of 3 inch wafer scale GaAs epitaxial wafer grown by molecular beam epitaxy for LSI process application were studied. The thickness and doping uniformity are characterized and discussed. The growth temperature and growth rate were $600^{\circ}C$ by pyrometer, and 1 $\mu$m/h, respectively. It was found that thickness and doping uniformity were 3.97% and 4.74% respectively across the full 3 inch diameter GaAs epitaxial layer. Also, ungated MESFETs have been fabricated and saturation current measurement showed 4.5% uniformity on 3 inch, epitaxial layer, but uniformity of threshold voltage increase up to 9.2% after recess process for MESFET device.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1648-1650
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• 1996

In present paper, Cu films $4{\mu}m$, thick were fabricated by dual deposition methods using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adherence, and reflection in Cu films [$Cu_{4-x}$(low resistivity) / $Cu_x$(high adherence) / Si- wafer] on the x thickness have been investigated. Cu films of $4{\mu}m$ thickness formed with dual deposition methods had the low electrical resistivity of about $2.6{\mu}{\Omega}{\cdot}cm$ and high adherence of about 700g/cm. In conclusion, it is possible for these films to be used for micro-devices.

• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.71-74
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• 2012

Uniformity of the wafer temperature is one of the important factors in etching process. Plasma, chucking force, backside helium pressure and the surface temperature of ESC(electrostatic chuck) affect the wafer temperature. ESC consists of several layers of structure. Each layer has own thermal resistance and the Si-adhesive layer has highest thermal resistance among them. In this work, the temperature distribution of ESC was analyzed by 3-D FEM with various defects and the thickness deviation of the Si-adhesive layer. The result with Si-adhesive layer with the low center thickness deviation shows modified temperature distribution of ESC surface.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.252.1-252.1
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• 2013

Hexagonal boron nitride (h-BN) is a two dimensional material which has high band-gap, flatness and inert properties. This properties are used various applications such as dielectric for electronic device, protective coating and ultra violet emitter so on. 1) In this report, we were growing h-BN sheet directly on sapphire 2"wafer. Ammonia borane (H3BNH3) and nickel were deposited on sapphire wafer by evaporate method. We used nickel film as a sub catalyst to make h-BN sheet growth. 2) During annealing process, ammonia borane moved to sapphire surface through the nickel grain boundary. 3) Synthesized h-BN sheet was confirmed by raman spectroscopy (FWHM: ~30cm-1) and layered structure was defined by cross TEM (~10 layer). Also we controlled number of layer by using of different nickel and ammonia borane thickness. This nickel film supported h-BN growth method may propose fully and directly growing on sapphire. And using deposited ammonia borane and nickel films is scalable and controllable the thickness for h-BN layer number controlling.