• 한국세라믹학회지
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• 제46권1호
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.7-8
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• 2005

The pseudo MOSFET measurement technique has been a simple and rapid method for characterization of SOI wafers without any device fabrication process. We adopted the pseudo MOSFET technique to examine the surface silicon film thickness dependence of electrical properties of SOI wafer. The measurements showed that turn-on voltage increased and electron mobility decreased as the SOI film thickness was reduced in the SOI film thickness of less than 20 nm region.

• Bulletin of the Korean Chemical Society
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• 제26권6호
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• pp.966-970
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• 2005

To measure the thickness of liquid films from 10 to 60 ${\mu}m$, we used photochromic dye activation. And we used silicone oil with 10 centi-Stokes and commercial photochromic dyes. To make films with exact and known thicknesses, we used two glass wafers. A film formed between two wafers after placing a drop of liquid of known volume on one wafer and covering the other. The film thickness could be estimated from the diameter of wafer and the dropped liquid volume. To quantitatively evaluate the result, captured the images using digital camera then analyzed the images using the image tool. The gray scale intensity using the captured images of activated dye with these thicknesses showed the repeatability below ${\pm}$ 1.0% when measured with a silicone oil solution containing 0.1% SO and SO-ANTH dyes. And we showed that photochromic dye activation method could be used to measure our liquid film thickness ranges.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2449-2452
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• 2007

Hot spots on thin wafers of IC packages are becoming important issues in thermal and electrical engineering fields. To investigate these hot spots, we developed a Diode Temperature Sensor Array (DTSA) that consists of an array of 32 ${\times}$32 diodes (1,024 diodes) in a 8 mm ${\times}$ 8 mm surface area. To know specifically the hot spot temperature which is affected by the chip thickness and a generated power, we made the DTSA chips, which have 21.5 ${\mu}m$, 31 ${\mu}m$, 42 ${\mu}m$, 100 ${\mu}m$, 200 ${\mu}m$, and 400 ${\mu}m$ thickness using the CMP process. And we conducted the experiment using various heater power conditions (0.2 W, 0.3 W, 0.4 W, 0.5 W). In order to validate experimental results, we performed a numerical simulation. Errors between experimental results and numerical data are less than 4%. Finally, we proposed a correlation for the hot spot temperature as a function of the generated power and the wafer thickness based on the results of the experiment. This correlation can give an easy estimate of the hot spot temperature for flip chip packaging when the wafer thickness and the generated power are given.

• Journal of Welding and Joining
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• 제19권3호
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• pp.305-310
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• 2001

UBM-coated Si-wafer was fluxlessly soldered with glass substrate in $N_2$ atmosphere using plasma cleaning method. The bulk Sn-37wt.%Pb solder was rolled to the sheet of $100\mu\textrm{m}$ thickness in order to bond a solder disk by fluxless 1st reflow process. The oxide layer on the solder surface was analysed by AES(Auger Electron Spectroscopy). Through rolling, the oxide layer on the solder surface became thin, and it was possible to bond a solder disk on the Si-wafer with fluxless process in $N_2$ gas. The Si-wafer with a solder disk was plasma-cleaned in order to remove oxide layer formed during 1st reflow and soldered to glass by 2nd reflow process without flux in $N_2$ atmosphere. The thickness of oxide layer decreased with increasing plasma power and cleaning time. The optimum plasma cleaning condition for soldering was 500W 12min. The joint was sound and the thicknesses of intermetallic compounds were less than $1\mu\textrm{m}$.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 추계학술대회 초록집
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• pp.50.1-50.1
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• 2010

결정질 실리콘 태양전지의 원가에서 Wafer는 60~70%의 매우 높은 비중을 차지하고 있다. 많은 연구들이 원가 절감을 위하여 Wafer의 두께를 감소시키는 것에 집중하고 있다. 그러나 Wafer 두께의 감소는 태양전지의 효율 감소와 공정 진행 중에 파손율이 상승하는 등의 문제가 발생한다. 이에 본 논문에서는 결정질 태양전지 구조 중에서 24.7% 이상의 최고 변환 효율을 갖는 PERL(Passivated Emitter, Rear Locally diffuse) 구조를 대상으로 wafer 두께 감소에 따른 변환 효율 감소의 원인과 해결 방안을 제시하고자 한다. Simulation으로 확인한 결과 370 um 두께의 wafer에서 24.2 %의 효율은 50 um 두께의 wafer에서는 20.8 %로 감소함을 확인할 수 있었다. 얇아진 wafer에서 감소한 효율을 개선하기 위하여 후면 recombination velocity, 후면 fixed charge density, 후면 산화막 두께 등을 다양화하여, 각각의 경우에 대한 cell의 효율 변화를 살펴보았다. 그 결과 후면 recombination velocity, 후면 fixed charge density, 후면 산화막 두께를 최적화 하여, 각각 2.8 %p, 1.5 %p, 2.8 %p의 효율 개선 효과를 얻었다. 위 세 가지 효과를 동시에 적용하면 50 um wafer에서 370 um wafer 효율의 결과와 근접한 24.2 %의 효율을 얻을 수 있었다. 향후에는 위의 결과를 바탕으로 실제 실험을 통하여 확인할 계획이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• 한국전기전자재료학회논문지
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• 제23권5호
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• pp.358-363
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• 2010

The polishing pad is important element for polishing characteristic such as material removal rate(MRR) and within wafer non-uniformity(WIWNU) in the chemical mechanical planarization(CMP). The result of the viscoelasticity measurement shows that 1st elastic modulus is increased and 2nd elastic modulus is decreased when the top pad is thickened. The finite element analysis(FEA) was conducted to predict characteristic of polishing behavior according to the pad thickness. The result of polishing experiment was similar with the FEA, and it shows that the 1st elastic modulus affects instantaneous deformation of pad related to MRR. And the 2nd elastic modulus has an effect on WIWNU due to the viscoelasticity deformation of pad.