• 대한산업공학회지
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• 제36권1호
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• 한국전기전자재료학회논문지
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• 제15권11호
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• International Journal of Control, Automation, and Systems
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• 제4권3호
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• pp.372-381
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• 2006

The purpose of this study was to develop a process management system to manage ingot fabrication and improve ingot quality. The ingot is the first manufactured material of wafers. Trace parameters were collected on-line but measurement parameters were measured by sampling inspection. The quality parameters were applied to evaluate the quality. Therefore, preprocessing was necessary to extract useful information from the quality data. First, statistical methods were used for data generation. Then, modeling was performed, using the generated data, to improve the performance of the models. The function of the models is to predict the quality corresponding to control parameters. Secondly, rule extraction was performed to find the relation between the production quality and control conditions. The extracted rules can give important information concerning how to handle the process correctly. The dynamic polynomial neural network (DPNN) and decision tree were applied for data modeling and rule extraction, respectively, from the ingot fabrication data.

• 한국기계가공학회지
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• 제14권6호
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• pp.104-110
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• 2015

LED has added value as a lighting source in the illuminating industry because of its high efficiency and low power consumption. In LED production processes, the chip cutting process, which mainly uses a scribing process with a laser has an effect on quality and productivity of LED. This scribing process causes problems like heat deformation, decreasing strength. The inner laser method, which makes a void in wafer and induces self-cracking, can overcome these problems. In this paper, cutting sapphire wafer for fabricating LED chip using the inner laser scribing process is proposed and evaluated. The aim is to settle basic experiment conditions, determine parameters of cutting, and analyze the characteristics of cutting by means of experimentation.

• 센서학회지
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• 제1권2호
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• pp.131-145
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• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 춘계학술대회
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• pp.1078-1082
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• 2003

A feasibility study for the fabrication of master replication with nanostructures by Nanoimprint Lithography (NIL) was investigated for application of polymer Photonic Bandgap (PBG) devices used in photonic IC. Large area gratings of $9{\times}15(mm^2)$ with p = 400 nm was successfully embossed on PMMA on silicon wafer and the embossing parameters (temperature, pressure, time) were established. A precise control of $O_2$ plasma Reactive Ion Etching (RIE) process time allowed window opening over the whole area despite the presence of wafer bending. Master replication with aspect ratio 1 was successfully fabricated, but master replication with aspect ratio 3 needs to optimize parameters. All replications were done in a NIL process.

• 정보저장시스템학회논문집
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• 제1권2호
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• pp.175-181
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• 2005

SiOB is an essential part of slim optical pickup, where the silicon mirror, LD stand, silicon PD are integrated and LD is flip chip bonded. SiOB is fabricated with bulk micromachining. Especially the fabrication of silicon wafer with stepped concave areas has many extraordinary difficulties. As a matter of fact, experiences and knowledges are rare in the fabrication of the highly stepped silicon wafer. The difficulties occurring in the integration of PD and SiOB, and highly stepped patterning, and silicon mirror roughness and how-to-solve will be discussed.

• 센서학회지
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• 제28권4호
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• pp.251-255
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• 2019

We propose a two-step lithography process to minimize edge-bead issues caused by thick photoresist (PR) coating. In the conventional PR process, the edge bead can be efficiently removed by applying an edge-bead removal (EBR) process while rotating the silicon wafer at a high speed. However, applying conventional EBR to the production of desired PR mold with unique negative patterns cannot be used because a lower rpm of spin coating and a lower temperature in the soft bake process are required. To overcome this problem, a two-step lithography process was developed in this study and applied to the fabrication of a polydimethylsiloxane (PDMS) film having super-hydrophobic characteristics. Following UV exposure with a first photomask, the exposed part of the silicon wafer was selectively removed by applying a PR developer while rotating at a low rpm. Then, unique PR mold structures were prepared by employing an additional under-exposure process with a second mask, and the mold patterns were transferred to the PDMS. Results showed that the fabricated PDMS film based on the two-step lithography process reduced the height difference from 23% to 5%. In addition, the water contact angle was greatly improved by spraying of hydrophobic nanosilica on the dual-scaled PDMS surface.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.374-377
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• 2002

Magnetic field is necessary to control the convection of melted silicon and to improve the quality of the wafer in the 12inch silicon wafer growing process. Nowadays, superconducting magnet is used in this process. We fabricated and tested a saddle shaped superconducting magnet for 8inch silicon wafer growing system. And the protection circuits for HTS current lead and superconducting coil are designed and manufactured. In this paper, their manufacturing process and test results are introduced.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 2001년도 추계학술대회 논문집
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.