• 산업공학
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• 제12권3호
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• 대한산업공학회지
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• 제21권3호
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• pp.357-369
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• 1995

Wafer fabrication process is the most important and critical process in semiconductor manufacturing. The process is very complicated and hard to establish an efficient schedule due to its complexity. Furthermore, several performance indices such as due dates, throughput, cycle time and workstation utilizations are to be considered simultaneously for an efficient schedule, and some of these indices have negative correlations in performances each other. We develop an efficient heuristic scheduling algorithm; Hybrid Input Control Policy and Hybrid Dispatching Rule. Through numerical experiments, it is shown that the proposed Hybrid Scheduling Algorithm gives better performance compared with existing algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• 한국결정성장학회지
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• 제10권1호
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• pp.13-16
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• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 한국산학기술학회논문지
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• 제16권9호
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• pp.5748-5755
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• 2015

스크라이빙 공정은 LED 칩 생성을 위한 절단 공정으로 칩의 특성 및 생산량을 결정하는 중요한 공정이다. 기존의 기계적 방식 및 레이저 방식의 스크라이빙 공정은 칩의 열 변형 및 강도 저하, 절단 영역의 제한 등의 문제점이 있다. 이러한 문제를 해결하기 위해 웨이퍼 내부에 공극을 생성하여 자가 균열을 유도하는 내부 레이저 스크라이빙 공정이 연구되고 있으나 LED 칩 제작을 위한 사파이어 웨이퍼의 절단에 대한 연구는 미비한 실정이다. 본 논문은 LED 칩 제작에 사용되는 사파이어 웨이퍼의 내부 레이저 스크라이빙 공정을 적용하기 위해 주요 가공 변수를 정립하고 가공 실험을 통하여 절단 특성을 분석함으로써 내부 레이저 스크라이빙 시스템 구축을 위한 기초 가공 조건을 확립하였다.

• 지능정보연구
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• 제9권1호
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• pp.157-177
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• 2003

본 논문은 반도체 FAB공정의 수율개선 및 예측을 위해 데이터마이닝 기법을 적용한 사례를 소개한다. FAB 공정의 복잡성과 생산현장에서 수집되는 방대한 기술데이터로 인해 기존의 통계적 방법이나 엔지니어의 경험적 분석 방법만으로는 미처 파악하지 못하는 수율 저하 요인이 상당 수 존재한다. 본 논문은 먼저, FAB공정을 마친 웨이퍼에 불량 칩(chip)이 지리적으로 특정 위치에 집중적으로 발생하는 현상을 육안검사 대신 군집분석을 이용하여 데이터로부터 자동 판별할 수 있는 방법을 제안한다. 다음으로 연속패턴분석, 분류분석, RBF(Radial Base Function) 기법을 적용하여 수율 저하의 원인이 되는 문제 장비나 문제 파라미터를 신속, 정확하게 파악할 수 있도록 해 줄 뿐만 아니라 공정 진행 중인 제품의 미래 수율을 예측할 수 있도록 지원하는 방법을 제안한다. 또한 위 기법들을 반도체 FAB공정을 대상으로 국내 모 반도체 회사에서 정보시스템으로 구현한 Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis ＆ Up Support) 시스템을 소개한다.

• Transactions on Electrical and Electronic Materials
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• 제15권2호
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• 정보저장시스템학회논문집
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• 제2권3호
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.