• 유공압시스템학회논문집
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• 제8권3호
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• pp.14-20
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• 2011

This study aims at aligning multiple wafers to reduce wafer handling time in wafer processes. We designed a multilevel structure for a prealigner which can handle multiple wafer simultaneously in a system. The system consists of gripping parts, kinematic parts, vacuum chucks, pneumatic units, hall sensors and a DSP controller. Aligning procedure has two steps: mechanical gripping and notch finding. In the first step, a wafer is aligned in XY directions using 4-point mechanical contact. The rotational error can be found by detecting a signal in a notch using hall sensors. A dual prealigner was designed for 300mm wafers and constructed for a performance test. The accuracy was monitored by checking the movement of a notch in a machine vision. The result shows that the dual prealigner has enough performance as commercial products.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.211-213
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• 1999

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

• 반도체디스플레이기술학회지
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• 제11권2호
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• pp.33-38
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• 2012

The wafer positioning robot in the semiconductor industry is required to operate at high speed for the improvement of productivity. The residual vibration caused by the high speed of the wafer positioning robot, however, makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the improvement of the cycle time. The followings are the process for the reduction and the improvement; 1) System modeling of the wafer positioning robot, 2) Verification of dynamic characteristics of the wafer positioning robot, 3) Input shaping plan using impulse response reiteration, 4) Simulation test using SIMULINK program, 5) Analysis of result.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2005년도 추계학술대회논문집
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• pp.559-563
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• 2005

The wafer positioning robot used in the semiconductor industry is required to operate at high speed for the improvement of productivity. However, the residual vibration produced by the high speed of the wafer positioning robot makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the optimization of the cycle time. The followings are the process for the reduction and the optimization; 1)System modeling of wafer positioning robot, 2)Verification of dynamic characteristic of wafer positioning robot, 3)Input shaping plan using impulse response reiteration, 4)Simulation test using simulink, 6)Analysis of result.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• 한국산학기술학회논문지
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• 제5권5호
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• pp.458-461
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• 2004

본 논문에서는 Si wafer와 Cu사이의 밀착력을 증가시키기 위해 Si wafer전처리 후 plasma와 SAMs처리 방법에 의한 Cu도금의 형성에 관한 방법을 설명하였다. Si wafer를 Piranha solution과 $0.5{\%}$ HF처리 후 유기박막인 SAMs과 plasma를 이용하는 방법으로 wafer와 Cu층 사이의 밀착력을 증가시켰다. 도금층의 밀착력은 scratch test 로 측정하였으며 , AFM을 이용해 시편에 형성된 패턴의 형태를 관찰하고 SEM과 EDS를 이용해 시편의 조직을 관찰하였다. 그 결과 Si wafer를 $O_{2}, He, SAMs$를 혼합처리 했을 때 밀착성이 가장 우수하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.40-44
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• 2008

The interfacial adhesion energy between resist and a substrate is very important due to resist pull-off problems during separation of mold from a substrate in nanoimprint process. And effect of substrate surface roughness on interfacial adhesion energy is very important. In this paper, we have treated glass wafer surface using $CF_4$ gas for increase surface roughness and it has tested interfacial adhesion properties of UV resin/glass substrate interfaces by 4 point bending test. The interfacial adhesion energies by bare, 30, 60 and 90 sec surface treatments are 0.62, 1.4, 1.36 and 2 $J/m^2$, respectively. The test results showed quantitative comparisons of interfacial fracture energy (G) effect of glass wafer surface roughness.

• 대한기계학회논문집B
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• 제30권4호
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• 융복합기술연구소 논문집
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• 제5권1호
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• pp.13-17
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• 2015

In wafer level molding progress, the thermal releasing failure phenomenon is shown up as the important problem. This phenomenon can cause the problem including the warpage, crack of the molded wafer. The thermal releasing failure is due to the insufficiency of adhesion strength degradation of the molding tape. To solve this problem, we studied experimental method increasing the release property of the molding tape through the plasma surface treatment on the wafer substrate. In this research, the vacuum plasma treatment system is used for release property improvement of the molding tape and controls the operating condition of the hydrophilic($O_2$, 100kW, 10min) and hydrophobic($C_2F_6$, 200kW, 10min). In order to perform the peeling test for measuring the releasing force precisely, we remodel the micro scale material property evaluation system developed by Korea institute of industrial technology. In case of hydrophilic surface treatment on the wafer substrate, we can figure out the releasing property of molding tape increase. In order to grasp the effect that it reaches to the release property increase when repeating the hydrophilic treatment, we make an experiment with twice treatment and get the result to increase about 12%. We find out the hydrophilic surface treatment method using plasma can improve releasing property of molding tape in the wafer level molding process.

• 반도체디스플레이기술학회지
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• 제2권2호
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.