• Korean Chemical Engineering Research
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• v.46 no.3
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• pp.619-625
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• 2008

The effects of thermal cycling on residual stresses in both inorganic passivation/insulating layer that is deposited by plasma enhanced chemical vapor deposition (PECVD) and organic thin film that is used as a bonding adhesive are evaluated by 4 point bending method and wafer curvature method. $SiO_2/SiN_x$ and BCB (Benzocyclobutene) are used as inorganic and organic layers, respectively. A model about the effect of thermal cycling on residual stress and bond strength (Strain energy release rate), $G_c$, at the interface between inorganic thin film and organic adhesive is developed. In thermal cycling experiments conducted between $25^{\circ}C$ and either $350^{\circ}C$ or $400^{\circ}C$, $G_c$ at the interface between BCB and PECVD $ SiN_x $ decreases after the first cycle. This trend in $G_c$ agreed well with the prediction based on our model that the increase in residual tensile stress within the $SiN_x$ layer after thermal cycling leads to the decrease in $G_c$. This result is compared with that obtained for the interface between BCB and PECVD $SiO_2$, where the relaxation in residual compressive stress within the $SiO_2$ induces an increase in $G_c$. These opposite trends in $G_cs$ of the structures including either PECVD $ SiN_x $ or PECVD $SiO_2$ are caused by reactions in the hydrogen-bonded chemical structure of the PECVD layers, followed by desorption of water.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of Mechanical Science and Technology
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• v.19 no.2
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• pp.682-691
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• 2005

This paper describes the design, fabrication, and testing of a microturbine developed at Seoul National University. Here, the term 'microturbine' refers to a radial turbine with a diameter on the order of a centimeter. Such devices can be used to transmit power for various systems. The turbine is designed using a commercial CFD code, and it has a design flow coefficient of 0.238 and work coefficient of 0.542. It has 31 stator blades and 24 rotor blades. A hydrodynamic journal bearing and hydrostatic thrust bearings counteract radial and axial forces on the rotor. The test turbine consists of a stack of five wafers and is fabricated by MEMS technology, using photolithography, DRIE, and bonding processes. The first, second, fourth, and fifth layers contain plumbing, and hydrostatic axial thrust bearings for the turbine. The third wafer contains the turbine's stator, rotor, and hydrodynamic journal bearings. Furthermore, a turbine test facility containing a flow control system and instrumentation has been designed and constructed. In performance tests, a maximum rotation speed of 11,400 rpm and flow rate of 16,000 sccm have been achieved.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.234-234
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• 2010

The PR transitions in asymmetric dot-in-double-quantum-well (DdWELL) photodetector is identified by bias-dependent spectral behaviors. Discrete n-i-n infrared photodetectors were fabricated on a 30-period asymmetric InAs-QD/[InGaAs/GaAs]/AlGaAs DdWELL wafer that was prepared by MBE technique. A 2.0-monolayer (ML) InAs QD ensemble was embedded in upper combined well of InGaAs/GaAs and each stack is separated by a 50-nm AlGaAs barrier. Each pixel has circular aperture of 300 um in diameter, and the mesa cell ($410{\times}410\;{\mu}m^2$) was defined by shallow etching. PR measurements were performed in the spectral range of $3{\sim}13\;{\mu}m$ (~ 100-400 meV) by using a Fourier-transform infrared (FTIR) spectrometer and a low-noise preamplifier. The asymmetric photodetector exhibits unique transition behaviors that near-/far-infrared (NIR/FIR) photoresponse (PR) bands are blue/red shifted by the electric field, contrasted to mid-infrared (MIR) with no dependence. In addition, the MIR-FIR dual-band spectra change into single-band feature by the polarity. A four-level energy band model is proposed for the transition scheme, and the field dependence of FIR bands numerically calculated by a simplified DdWELL structure is in good agreement with that of the PR spectra. The wavelength shift by the field strength and the spectral change by the polarity are discussed on the basis of four-level transition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.