• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.323-327
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• 2004

The bubble flow from the wafer surface during plating process was studied in this paper. The plating shape in the opening of photoresist becomes gradated shape in the fountain plating system, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and ${\alpha}-step$. In ${\alpha}-step$ measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16.6%,\;{\pm}4%$ respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.147-148
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.233-234
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• 2011

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.346.2-346.2
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• 2016

The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

• Tribology and Lubricants
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• v.26 no.4
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• pp.219-223
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• 2010

Despite the increasing need of nanometer-scale accuracy in abrasive machining using ultrasmall particles such as abrasive jet and chemical mechanical polishing(CMP), the process mechanism is still unknown. Based on the background, research on the effects of various process parameters on the machined surface at abrasive machining was motivated and performed by using finite element analysis where the effect of slurry fluid flow involved. The effect of particle shape on the machined surface during particle-surface collision was discussed in this paper. The results from FEA simulation revealed that any damage or defect generation on machined surface by the impact may occur only if the particle has enough impact energy. Therefore, it could be concluded that generation of the defects and damage on the wafer surface after CMP process was mainly due to direct contact of the 3 bodies, i.e., pad-particle-wafer.

• Journal of Power System Engineering
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• v.5 no.2
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• pp.36-42
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• 2001

This paper deals with finite element analyses of residual stresses causing popping up which are induced in micromachining processes of a microaccelerometer sensors. The paddle of the micro accelerometer sensor is designed symmetric with respect to the direction of the beam. After heating the tunnel gap up to 100 degree and get it through the cooling process and the additional beam up to 80 degree and get it through the cooling process. We learn the thermal internal stresses of each shape and compare the results with each other, after heating the tunnel gap up to 400 degree during the Pt deposition process. Finally we find the optimal shape which is able to minimize the internal stresses of microaccelerometer sensor. We want to seek after the real cause of this pop up phenomenon and diminish this by change manufacturing processes of microaccelerometer sensor by electrostatic force.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.39-43
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• 2010

According to recent changes in industry for the semiconductor device, a gap between patterns in wafer is getting narrow. And this narrow gap makes a failure of uniform deposition between center and edge on the wafer. In this paper, for solving this problem, we analyze and manipulate the gas flow inside of the HDP CVD chamber by using CFD(Computational Fluid Dynamics). This simulation includes design manipulations in heights of the chamber and shape of center nozzle in the upper side of the chamber. The result of simulation shows 1.28 uniformity which is lower 3% than original uniformity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.4
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• pp.560-566
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• 1997

Dislocation behavior in the ZnSe crystal grown by seeded vapor transport was investigated. Etch pit shape with the ZnSe plane and dislocation arrangement were shown. Also the variation of the dislocation density in the crystal was disclosed. The dislocation density along the lateral growth direction was not changed but the dislocation density along the vertical growth direction was reduced as the crystal grew. The average dislocation density of the grown crystal was $4{\times}10^4 /\textrm{cm}^2$.