• 제목/요약/키워드: Wafer Shape

검색결과 135건 처리시간 0.029초

경사진 전극링을 이용한 고균일도의 미세 솔더범프 형성 (Formation of fine pitch solder bump with high uniformity by the tilted electrode ring)

  • 주철원;이경호;민병규;김성일;이종민;강영일
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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    • pp.323-327
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    • 2004
  • The bubble flow from the wafer surface during plating process was studied in this paper. The plating shape in the opening of photoresist becomes gradated shape in the fountain plating system, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and ${\alpha}-step$. In ${\alpha}-step$ measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16.6%,\;{\pm}4%$ respectively.

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극저온 식각장비용 정전척 쿨링 패스 온도 분포 해석 (Temperature Analysis of Electrostatic Chuck for Cryogenic Etch Equipment)

  • 두현철;홍상진
    • 반도체디스플레이기술학회지
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    • 제20권2호
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    • pp.19-24
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    • 2021
  • As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

A Study on Blister Formation and Electrical Characteristics with Varied Annealing Condition of P-doped Amorphous Silicon

  • 최성진;김가현;강민구;이정인;김동환;송희은
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.346.2-346.2
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    • 2016
  • The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

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입자연마가공에서의 입자 형상의 영향에 대한 고찰 (A Closer Look at the Effect of Particle Shape on Machined Surface at Abrasive Machining)

  • 김동균;성인하
    • Tribology and Lubricants
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    • 제26권4호
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    • pp.219-223
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    • 2010
  • Despite the increasing need of nanometer-scale accuracy in abrasive machining using ultrasmall particles such as abrasive jet and chemical mechanical polishing(CMP), the process mechanism is still unknown. Based on the background, research on the effects of various process parameters on the machined surface at abrasive machining was motivated and performed by using finite element analysis where the effect of slurry fluid flow involved. The effect of particle shape on the machined surface during particle-surface collision was discussed in this paper. The results from FEA simulation revealed that any damage or defect generation on machined surface by the impact may occur only if the particle has enough impact energy. Therefore, it could be concluded that generation of the defects and damage on the wafer surface after CMP process was mainly due to direct contact of the 3 bodies, i.e., pad-particle-wafer.

SOI웨이퍼를 이용한 마이크로가속도계 센서의 열응력해석(I) (Analyses Thermal Stresses for Microaccelerometer Sensors using SOI Wafer(I))

  • 김옥삼
    • 동력기계공학회지
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    • 제5권2호
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    • pp.36-42
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    • 2001
  • This paper deals with finite element analyses of residual stresses causing popping up which are induced in micromachining processes of a microaccelerometer sensors. The paddle of the micro accelerometer sensor is designed symmetric with respect to the direction of the beam. After heating the tunnel gap up to 100 degree and get it through the cooling process and the additional beam up to 80 degree and get it through the cooling process. We learn the thermal internal stresses of each shape and compare the results with each other, after heating the tunnel gap up to 400 degree during the Pt deposition process. Finally we find the optimal shape which is able to minimize the internal stresses of microaccelerometer sensor. We want to seek after the real cause of this pop up phenomenon and diminish this by change manufacturing processes of microaccelerometer sensor by electrostatic force.

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HDP CVD 챔버 형상 변화에 따른 가스 유동 균일성에 대한 연구 (Study for Gas Flow Uniformity Through Changing of Shape At the High Density Plasma CVD (HDP CVD) Chamber)

  • 장경민;김진태;홍순일;김광선
    • 반도체디스플레이기술학회지
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    • 제9권4호
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    • pp.39-43
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    • 2010
  • According to recent changes in industry for the semiconductor device, a gap between patterns in wafer is getting narrow. And this narrow gap makes a failure of uniform deposition between center and edge on the wafer. In this paper, for solving this problem, we analyze and manipulate the gas flow inside of the HDP CVD chamber by using CFD(Computational Fluid Dynamics). This simulation includes design manipulations in heights of the chamber and shape of center nozzle in the upper side of the chamber. The result of simulation shows 1.28 uniformity which is lower 3% than original uniformity.

경사진 전극링에 의한 웨이퍼레벨패키지용 고균일도의 솔더범프 형성 (Formation of high uniformity solder bump for wafer level package by tilted electrode ring)

  • 주철원;이경호;민병규;김성일;이종민;강영일;한병성
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.366-369
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    • 2003
  • The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

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ZnSe 단결정내에서의 전위거동 (Dislocation behavior in the ZnSe crystal)

  • 이성국;박성수;김준홍;한재용;이상학
    • 한국결정성장학회지
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    • 제7권4호
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    • pp.560-566
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    • 1997
  • Seeded vapor transport법에 의해 성장된 ZnSe 결정내에서 전위거동을 살펴보았다. (111)과 (100) ZnSe wafer의 etch pit 형상을 관찰하였고 성장된 결정이 높은 전위밀도를 가지면 전위들이 lineage와 cellular 두 가지 형태로 배열됨을 알았다. Seed로부터 측방성장된 부위에서 전위밀도의 변화는 없었으나 수직 성장방향으로는 전위밀도가 감소하였고, 같은 wafer내에서 전위밀도는 wafer center 지역의 전위밀도가 edge부위의 전위밀도 보다 낮았다. 성장된 결정의 평균 전위밀도는 $4{\times}10^4 /\textrm{cm}^2$이었다.

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