• 제목/요약/키워드: Wafer Processing

검색결과 232건 처리시간 0.024초

Image Processing and Deep Learning-based Defect Detection Theory for Sapphire Epi-Wafer in Green LED Manufacturing

  • Suk Ju Ko;Ji Woo Kim;Ji Su Woo;Sang Jeen Hong;Garam Kim
    • 반도체디스플레이기술학회지
    • /
    • 제22권2호
    • /
    • pp.81-86
    • /
    • 2023
  • Recently, there has been an increased demand for light-emitting diode (LED) due to the growing emphasis on environmental protection. However, the use of GaN-based sapphire in LED manufacturing leads to the generation of defects, such as dislocations caused by lattice mismatch, which ultimately reduces the luminous efficiency of LEDs. Moreover, most inspections for LED semiconductors focus on evaluating the luminous efficiency after packaging. To address these challenges, this paper aims to detect defects at the wafer stage, which could potentially improve the manufacturing process and reduce costs. To achieve this, image processing and deep learning-based defect detection techniques for Sapphire Epi-Wafer used in Green LED manufacturing were developed and compared. Through performance evaluation of each algorithm, it was found that the deep learning approach outperformed the image processing approach in terms of detection accuracy and efficiency.

  • PDF

접촉전도와 반투명 복사가 반도체 웨이퍼의 CVD 공정 중 열전달에 미치는 영향 (Effect of Contact Conductance and Semitransparent Radiation on Heat Transfer During CVD Process of Semiconductor Wafer)

  • 윤용석;홍혜정;송명호
    • 대한기계학회논문집B
    • /
    • 제32권2호
    • /
    • pp.149-157
    • /
    • 2008
  • During CVD process of semiconductor wafer fabrication, maintaining the uniformity of temperature distribution at wafer top surface is one of the key factors affecting the quality of final products. Effect of contact conductance between wafer and hot plate on predicted temperature of wafer was investigated. The validity of opaque wafer assumption was also examined by comparing the predicted results with Discrete Ordinate solutions accounting for semitransparent radiative characteristics of silicon. As the contact conductance increases predicted wafer temperature increases and the differences between maximum and minimum temperatures within wafer and between wafer and hot plate top surface temperatures decrease. The opaque assumption always overpredicted the wafer temperature compared to semitransparent calculation. The influences of surrounding reactor inner wall temperature and hot plate configuration are then discussed.

A New Smart Stacking Technology for 3D-LSIs

  • Koyanagi Mitsu
    • 한국마이크로전자및패키징학회:학술대회논문집
    • /
    • 한국마이크로전자및패키징학회 2005년도 ISMP
    • /
    • pp.89-110
    • /
    • 2005
  • A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

  • PDF

웨이퍼 오류 패턴 인식 시뮬레이션 (Wafer Fail Pattern Classification Simulation)

  • 김상진;한영신;이칠기
    • 한국시뮬레이션학회논문지
    • /
    • 제12권3호
    • /
    • pp.13-20
    • /
    • 2003
  • Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

  • PDF

GaN 웨이퍼의 다이싱을 위한 스크라이빙 머신의 개발 (Development of Scribing Machine for Dicing of GaN Wafer)

  • 차영엽;고경용
    • 제어로봇시스템학회논문지
    • /
    • 제8권5호
    • /
    • pp.419-424
    • /
    • 2002
  • After the patterning and probe process of wafer have been achieved, the dicing processing is necessary to separate chips from a wafer. The dicing process cuts a semiconductor wafer to lengthwise and crosswise directions to make many chips. The existing general dicing method is the mechanical cutting using a narrow circular rotating blade impregnated diamond particles or laser cutting. Inferior goods can be made by the mechanical or laser cutting unless several parameters such as blade, wafer, cutting water and cutting conditions are properly set. Moreover, we can not apply these general dicing method to that of GaN wafer, because the GaN wafer is harder than general semiconductor wafers such as GaAs, GaAsP, AIGaAs and so forth. In order to overcome these problems, this paper describes a new wafer dicing method using fixed diamond scriber and precision servo mechanism.

반도체 웨이퍼의 스트레스 측정을 위한 공정 및 표면 검사시스템 구현 (Implementation of process and surface inspection system for semiconductor wafer stress measurement)

  • 조태익;오도창
    • 대한전자공학회논문지SD
    • /
    • 제45권8호
    • /
    • pp.11-16
    • /
    • 2008
  • 본 논문에서는 먼저 RTP(Rapid Thermal Processor) 장치를 스트레스 측정에 용이한 구조로 제작하고 PC에서 통합 공정관리 시스템을 설계하였다. 다음으로는 Large deformation 이론을 바탕으로 반도체 웨이퍼 표면의 변형검사를 위한 레이져 인터페로미터리를 구성하였다. 궁극적으로 이러한 레이져장치로부터 웨이퍼 표면의 영상을 추출하고 세선화, 블록화 그리고 스트레스 분포도의 순서로 영상처리 하여 스트레스로 인한 웨이퍼 표면의 변형을 검사하였다. 실험을 하기 위해 변형이 이루어지도록 웨이퍼의 후면을 1mm정도 갈아낸 후 약 1000도에서 $3\sim4$회 열처리를 수행하였으며, 열처리를 가한 영상과 가하지 않은 영상을 통하여 웨이퍼 열처리 후 심각한 변형이 이루어졌음을 알 수 있었다.

매엽식 세정장비의 동작순서 시뮬레이션 및 웨이퍼 처리량 측정에 관한 연구 (Study on Measurement of Wafer Processing Throughput and Sequence Simulation of SWP(Single Wafer Process) Cleaning Equipment)

  • 선복근;한광록
    • 전자공학회논문지CI
    • /
    • 제42권5호
    • /
    • pp.31-40
    • /
    • 2005
  • 본 연구에서는 웨이퍼의 식각, 세정, 연마 공정에 사용되는 매엽식 세정장비의 동작순서의 시뮬레이션과 단위 시간당 처리량 측정 방법에 대해 연구한다. 유한상태기계를 바탕으로 스케쥴링 알고리즘에 따른 로봇의 상태를 정의하여 시뮬레이션 모델을 구축하였으며, 이에 따른 시뮬레이션 수행을 통해 세정장비의 시간당 처리량을 측정하였다. 본 연구에서 제시한 시뮬레이션 기법을 통해 레시피와 로봇의 동작속도에 따라 세정장비의 단위시간당 처리량을 측정하고, 처리량을 극대화 할 수 있는 레시피와 로봇의 동작순서를 찾아낼 수 있다.

웨이퍼 본딩 공정을 위한 3채널 비전 얼라이너 개발 (Development of The 3-channel Vision Aligner for Wafer Bonding Process)

  • 김종원;고진석
    • 반도체디스플레이기술학회지
    • /
    • 제16권1호
    • /
    • pp.29-33
    • /
    • 2017
  • This paper presents a development of vision aligner with three channels for the wafer and plate bonding machine in manufacturing of LED. The developed vision aligner consists of three cameras and performs wafer alignment of rotation and translation, flipped wafer detection, and UV Tape detection on the target wafer and plate. Normally the process step of wafer bonding is not defined by standards in semiconductor's manufacturing which steps are used depends on the wafer types so, a lot of processing steps has many unexpected problems by the workers and environment of manufacturing such as the above mentioned. For the mass production, the machine operation related to production time and worker's safety so the operation process should be operated at one time with considering of unexpected problem. The developed system solved the 4 kinds of unexpected problems and it will apply on the massproduction environment.

  • PDF

피코초 펄스 레이저를 이용한 사파이어 웨이퍼 스크라이빙에 관한 연구 (A Study on Sapphire Wafer Scribing Using Picosecond Pulse laser)

  • 문재원;김도훈
    • 한국레이저가공학회지
    • /
    • 제8권2호
    • /
    • pp.7-12
    • /
    • 2005
  • The material processing of UV nanosecond pulse laser cannot be avoided the material shape change and contamination caused by interaction of base material and laser beam. Nowadays, ultra short pulse laser shorter than nanosecond pulse duration is used to overcome this problem. The advantages of this laser are no heat transfer, no splashing material, no left material to the adjacent material. Because of these characteristics, it is so suitable for micro material processing. The processing of sapphire wafer was done by UV 355nm, green 532nm, IR 1064nm. X-Y motorized stage is installed to investigate the proper laser beam irradiation speed and cycles. Also, laser beam fluence and peak power are calculated.

  • PDF

최적 dechucking 시스템 구현에 관한 연구 (A Study on the Implementation of Optimized Dechucking System)

  • 서종완;서희석;신명철
    • 조명전기설비학회논문지
    • /
    • 제21권5호
    • /
    • pp.106-111
    • /
    • 2007
  • 반도체 공정에서 각 단계별 과정을 거친 후 dechucking시 wafer가 ESC(Electrostatic Chuck)로부터 방전되지 못하고, 잔류되어 있는 극성을 띤 전하(Electric charge)들에 의해 wafer와 ESC사이에 인력이 발생하여 wafer의 sliding, popping 및 wafer broken 등의 문제가 발생한다. 본 논문에서는 wafer와 ESC의 구성을 capacitor를 이용하여 modeling하고, PSpice를 사용하여 chucking system에 의한 wafer의 대전 현상을 모의하고 그 결과를 바탕으로 잔류전하를 방전시키기 위한 여러 가지 방법을 검토하여 최적의 잔류전하 제거 기법을 제시한다. 즉 별도의 전압원을 사용하여 (+)와 (-)를 교번하는 구형파를 인가함과 아울러 일정시간 동안 Plasma내에서 스위칭시킴으로써 ESC나 wafer에 charge되어 있는 극성을 띤 전하들을 중화(Neutralize) 시키도록 하였다. 그리고 이를 실제 하드웨어로 구현하여 실 공정에 적용한 결과를 제시한다.