• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.65-69
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• 2019

The cure properties of ethoxysilyl diglycidyl isocyanurate(Ethoxysilyl-DGIC) and ethylsilyl diglycidyl isocyanurate (Ethylsilyl-DGIC) epoxy resin systems with a phenol novolac hardener were investigated for anticipating fan out-wafer level package(FO-WLP) applications, comparing with ethoxysilyl diglycidyl ether of bisphenol-A(Ethoxysilyl-DGEBA) epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The isocyanurate type epoxy resin systems represented the higher cure conversion rates comparing with bisphenol-A type epoxy resin systems. The Ethoxysilyl-DGIC epoxy resin system showed the highest cure conversion rates than Ethylsilyl-DGIC and Ethoxysilyl-DGEBA epoxy resin systems. It can be figured out by kinetic parameter analysis that the highest conversion rates of Ethoxysilyl-DGIC epoxy resin system are caused by higher collision frequency factor. However, the cure conversion rate increases of the Ethylsilyl-DGEBA comparing with Ethoxysilyl-DGEBA are due to the lower activation energy of Ethylsilyl-DGIC. These higher cure conversion rates in the isocyanurate type epoxy resin systems could be explained by the improvements of reaction molecule movements according to the compact structure of isocyanurate epoxy resin.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.29-33
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• 2019

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• Journal of the Semiconductor & Display Technology
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• v.19 no.1
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• pp.29-35
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• 2020

The cure characteristics of three kinds of naphthalene type epoxy resins(NET-OH, NET-MA, NET-Epoxy) with a 2-methyl imidazole(2MI) catalyst were investigated for preparing sheet epoxy molding compound(SEMC) for wafer level package(WLP) applications, comparing with diglycidyl ether of bisphenol-A(DGEBA) and 1,6-naphthalenediol diglycidyl ether(NE-16) epoxy resin. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The NET-OH epoxy resin represented an n-th order cure mechanism as like NE-16 and DGEBA epoxy resins, however, the NET-MA and NET-Epoxy resins showed an autocatalytic cure mechanism. The NET-OH and NET-Epoxy resins showed higher cure conversion rates than DGEBA and NE-16 epoxy resins, however, the lowest cure conversion rates can be seen in the NET-MA epoxy resin. Although the NETEpoxy and NET-MA epoxy resins represented higher cure reaction conversions comparing with DGEBA and NE-16 resins, the NET-OH showed the lowest cure reaction conversions. It can be figured out by kinetic parameter analysis that the lowest cure conversion rates of the NET-MA epoxy resin are caused by lower collision frequency factor, and the lowest cure reaction conversions of the NET-OH are due to the earlier network structures formation according to lowest critical cure conversion.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2217-2220
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• 2007

In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.